AD9633BCPZRL7-125 Ver la hoja de datos (PDF) - Analog Devices

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AD9633BCPZRL7-125

Quad, 12-Bit, 80 MSPS/105 MSPS/125 MSPS, Serial LVDS 1.8 V ADC

Analog Devices 

AD9633

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 7

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 14

AD9633-80 .................................................................................. 14

AD9633-105 ................................................................................ 16

AD9633-125 ................................................................................ 18

Equivalent Circuits ......................................................................... 21

Theory of Operation ...................................................................... 22

Analog Input Considerations.................................................... 22

Voltage Reference ....................................................................... 23

REVISION HISTORY

10/15—Rev. A to Rev. B

Added Note 4, Table 4 ...................................................................... 6

Changes to Digital Outputs and Timing Section ....................... 28

Changes to Clock Stability Considerations Section................... 39

9/14—Rev. 0 to Rev. A

Changes to Table 2............................................................................ 4

Added Propagation Delay Parameters of 1.5 ns (min)

and 3.1 ns (max); Table 4 ................................................................. 6

Changed tSSYNC from 0.24 ns Typ to 1.2 ns Min and Changed

tHSYNC from 0.40 ns Typ to −0.2 ns Min; Table 5 and Changes to

Figure 2 .............................................................................................. 7

Changes to Figure 3 and Figure 4 ................................................... 8

Changes to Figure 5 .......................................................................... 9

Data Sheet

Clock Input Considerations...................................................... 24

Power Dissipation and Power-Down Mode ........................... 26

Digital Outputs and Timing ..................................................... 27

Output Test Modes..................................................................... 30

Serial Port Interface (SPI).............................................................. 31

Configuration Using the SPI..................................................... 31

Hardware Interface..................................................................... 32

Configuration Without the SPI ................................................ 32

SPI Accessible Features.............................................................. 32

Memory Map .................................................................................. 33

Reading the Memory Map Register Table............................... 33

Memory Map Register Table..................................................... 34

Memory Map Register Descriptions........................................ 37

Applications Information .............................................................. 39

Design Guidelines ...................................................................... 39

Power and Ground Recommendations ................................... 39

Clock Stability Considerations ................................................. 39

Exposed Pad Thermal Heat Slug Recommendations............ 39

VCM............................................................................................. 39

Reference Decoupling................................................................ 39

SPI Port ........................................................................................ 39

Crosstalk Performance .............................................................. 40

Outline Dimensions ....................................................................... 41

Ordering Guide .......................................................................... 41

Changes to Pin 9 to Pin 14 and Pin 23 to Pin 28 Descriptions ....12

Changes to Figure 47 and Figure 48 ............................................ 21

Changes to Clock Input Options Section.................................... 24

Changes to Jitter Considerations Section.................................... 26

Changes to Digital Outputs and Timing Section ....................... 27

Changes to Table 12 ....................................................................... 29

Changes to Channel-Specific Registers Section ......................... 33

Changes to Output Phase (Register 0x16) Section .................... 37

Changes to Resolution/Sample Rate Override (Register 0x100)

Section.............................................................................................. 38

Added Clock Stability Considerations Section........................... 39

Updated Outline Dimensions ....................................................... 41

10/11—Revision 0: Initial Version

Rev. B | Page 2 of 41

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