AD9633BCPZRL7-125 Ver la hoja de datos (PDF) - Analog Devices
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AD9633BCPZRL7-125 Datasheet PDF : 42 Pages
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Data Sheet
AD9633
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
Typ
Max
0.2
AGND − 0.2
CMOS/LVDS/LVPECL
3.6
AVDD + 0.2
0.9
10
4
1.2
0
30
2
AVDD + 0.2
0.8
1.2
0
26
2
AVDD + 0.2
0.8
1.2
0
26
5
AVDD + 0.2
0.8
1.79
0.05
LVDS
290
345
400
1.15
1.25
1.35
Twos complement
Unit
V p-p
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
LVDS
Full
160
200
230
mV
Full
1.15
1.25
1.35
V
Twos complement
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO/OLM pins sharing the same connection.
Rev. B | Page 5 of 41
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