ISPLSI3256A Ver la hoja de datos (PDF) - Lattice Semiconductor

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componentes Descripción

Fabricante

ISPLSI3256A

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 3256A

Internal Timing Parameters1

Over Recommended Operating Conditions

PARAMETER #2

DESCRIPTION

Outputs

tob

tobs

46 Output Buffer Delay

47 Output Buffer Delay, Slew Limited Adder

toen

48 I/O Cell OE to Output Enabled

todis

49 I/O Cell OE to Output Disabled

Clocks

tgy0/1/2

50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line

tioy3/4

51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line

Global Reset

tgr

52 Global Reset to GLB and I/O Registers

tgoe

ttoe

53 Global OE Pad Buffer

54 Test OE Pad Buffer

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

-90

-70

-50

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

– 1.9 – 2.4 – 3.3 ns

– 11.9 – 12.4 – 13.3 ns

– 6.8 – 7.2 – 9.8 ns

– 6.8 – 7.2 – 9.8 ns

2.7 2.7 3.6 3.6 4.9 4.9 ns

0.7 3.7 1.2 5.2 1.6 7.0 ns

– 6.7 – 7.1 – 9.6 ns

– 2.3 – 2.8 – 3.7 ns

– 3.2 – 9.8 – 13.2 ns

Table 2-0037C/3256A

8

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