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ISPLSI3256A Ver la hoja de datos (PDF) - Lattice Semiconductor

Número de pieza
componentes Descripción
Fabricante
ISPLSI3256A
Lattice
Lattice Semiconductor Lattice
ISPLSI3256A Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Specifications ispLSI 3256A
External Switching Characteristics1, 2, 3
Over Recommended Operating Conditions
PARAMETER
TEST 5
COND.
#2
DESCRIPTION1
-90
-70
-50
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass
12.0 15.0 20.0 ns
tpd2
A 2 Data Prop. Delay
15.0 18.0 24.5 ns
fmax
A
3 Clk Frequency with Internal Feedback 3
90.0 77.0 57.0 MHz
fmax (Ext.)
4 Clk Frequency with Ext. Feedback
( ) 1
tsu2 + tco1
61.0 50.0 37.0
MHz
fmax (Tog.)
5 Clk Frequency, Max. Toggle4
125 83.0 63.0 MHz
tsu1
6 GLB Reg. Setup Time before Clk, 4 PT Bypass 8.0 9.5 12.5 ns
tco1
A 7 GLB Reg. Clk to Output Delay, ORP Bypass
7.5 9.0 12.0 ns
th1
8 GLB Reg. Hold Time after Clk, 4 PT Bypass
0.0 0.0 0.0 ns
tsu2
9 GLB Reg. Setup Time before Clk
9.0 11.0 15.0 ns
tco2
10 GLB Reg. Clk to Output Delay
9.0 10.5 14.0 ns
th2
11 GLB Reg. Hold Time after Clk
0.0 0.0 0.0 ns
tr1
A 12 Ext. Reset Pin to Output Delay
13.5 15.0 20.0 ns
trw1
13 Ext. Reset Pulse Duration
6.5 10.0 13.5 ns
tptoeen
B 14 Input to Output Enable
16.0 18.0 24.5 ns
tptoedis
C 15 Input to Output Disable
16.0 18.0 24.5 ns
tgoeen
B 16 Global OE Output Enable
10.0 11.0 13.5 ns
tgoedis
C 17 Global OE Output Disable
10.0 11.0 13.5 ns
ttoeen
B 18 Test OE Output Enable
10.0 17.0 23.0 ns
ttoedis
C 19 Test OE Output Disable
10.0 17.0 23.0 ns
twh
20 Ext. Synchronous Clk Pulse Duration, High
4.0 6.0 8.0 ns
twl
21 Ext. Synchronous Clk Pulse Duration, Low
4.0 6.0 8.0 ns
tsu3
22 I/O Reg Setup Time before Ext. Sync Clk (Y3, Y4) 5.0 5.0 7.0 ns
th3
23 I/O Reg Hold Time after Ext. Sync Clk (Y3, Y4) 0.0 0.0 0.0 ns
1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030C/3256A
6

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