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ISPLSI3256A

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 3256A

Internal Timing Parameters1

Over Recommended Operating Conditions

PARAMETER #2

DESCRIPTION

Inputs

tiobp

tiolat

tiosu

tioh

24 I/O Register Bypass

25 I/O Latch Delay

26 I/O Register Setup Time before Clock

27 I/O Register Hold Time after Clock

tioco

tior

28 I/O Register Clock to Out Delay

29 I/O Register Reset to Out Delay

GRP

tgrp

30 GRP Delay

GLB

t4ptbp

t4ptbp

31 4 Product Term Bypass Path Delay (Comb.)

32 4 Product Term Bypass Path Delay (Reg.)

t1ptxor

t20ptxor

txoradj

tgbp

33 1 Product Term/XOR Path Delay

34 20 Product Term/XOR Path Delay

35 XOR Adjacent Path Delay 3

36 GLB Register Bypass Delay

tgsu

tgh

37 GLB Register Setup Time before Clock

38 GLB Register Hold Time after Clock

tgco

39 GLB Register Clock to Output Delay

tgro

tptre

tptoe

tptck

40 GLB Register Reset to Output Delay

41 GLB Product Term Reset to Register Delay

42 GLB Product Term Output Enable to I/O Cell Delay

43 GLB Product Term Clock Delay

ORP

torp

torpbp

44 ORP Delay

45 ORP Bypass Delay

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

-90

-70

-50

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

– 1.9 – 2.4 – 3.3 ns

– 10.9 – 12.4 – 15.8 ns

5.7 – 6.2 – 8.6 – ns

-3.7 – -5.2 – -7.0 – ns

– 4.2 – 4.2 – 5.3 ns

– 2.8 – 3.6 – 4.9 ns

– 2.4 – 3.0 – 4.1 ns

– 4.8 – 5.9 – 7.6 ns

– 4.8 – 5.9 – 7.6 ns

– 5.4 – 6.4 – 8.8 ns

– 6.4 – 7.4 – 10.1 ns

– 6.9

– 0.1

– 8.1

– 0.1

– 11.1 ns

– 0.1 ns

1.0 – 1.8 – 2.4 – ns

4.8 – 6.0 – 8.2 – ns

– 1.6 – 1.8 – 2.2 ns

– 2.6

– 8.6

– 2.8 – 3.8 ns

– 10.5 – 14.2 ns

– 4.9 – 5.4 – 7.3 ns

2.8 5.3 3.2 6.3 4.3 8.5 ns

– 2.3 – 2.7 – 3.6 ns

– 0.9 – 1.2 – 1.6 ns

Table 2-0036C/3256A

7

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