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V96SSC-33LPREVB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

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V96SSC

Table 4: Signal Descriptions

Signal

Type Ra

Processor Interface Signals

Description

A31,A[26:16] I

High-order address lines from i960 processor. These signals are latched

internally by the V96SSC on the falling edge of ALE. Processor signals

A[30:27] are optional and may be routed to the V96SSC through the I/O

port pins (see below).

AD[15:0]

I/O

Z

Multiplexed address/data bus. For i960Jx based systems, the V96SSC

only uses the lower 16-bits of the AD[31:0] bus.

ALE

I

Address latch enable is connected to the i960 processor’s ALE pin. This

signal is connected to the internal address latches.

ADS

I

Address status is connected to the AS pin on the i960Sx and to ADS on

the i960Jx processors.

BE[1:0]

Low order byte enables. The BE[1:0] pins are inputs for accesses from

I/O

Z

external masters; they become outputs when the V96SSC is the bus

master. BE[3:2] are available through the I/O port pins for i960Jx sys-

tems (see below).

BLAST

I

End of burst indication from i960 processor.

W/R

I/O

Z

Write/Read indication from the i960 processor. W/R is driven during

V96SSC DMA operations to indicate the direction of the transfer.

HOLD

O L Hold request from the V96SSC DMA Controller to the i960 processor.

HLDA

I

Hold acknowledge from the i960 processor. This signal informs the

V96SSC that it is now the local bus master.

INT

O H Interrupt request output from the V96SSC interrupt controller.

READY

Data READY indication. The V96SSC returns READY to the i960 pro-

I/O

H

cessor when data is read/written to memory addresses under the

V96SSC’s control. The V96SSC also monitors the READY signal for all

bus accesses when the bus watch timer is enabled.

Bus transaction type. These signals are examined during the assertion

of AS, ADS or ALE to determine the type of external master initiating the

bus cycle.

BTYPE[1:0] I

BTYPE[1:0]

00

01

10

11

Master

i960SA/SB

PPC401Gx

i960JA/JD/JF (32-bit bus)

i960JA/JD/JF (16-bit bus)

Copyright © 1997, V3 Semiconductor Inc.

V96SSC Data Sheet Rev 2.3

9

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