V96SSC-33LPREVB1 Ver la hoja de datos (PDF) - QuickLogic Corporation

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V96SSC-33LPREVB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

Table 4: Signal Descriptions (cont’d)

Signal

BE2/IO10

BE3/IO11

A27/IO12

A28/IO13

A29/IO14

A30/IO15

Type R

Description

I/O

Z

Functions: Input port 2, Output port 2, byte enable 2 input/output (for use

w/32-bit masters), end-of-process indication for DMA channel 0.

I/O

Z

Functions: Input port 3, Output port 3, byte enable 3 input/output (for use

w/32-bit masters), end-of-process indication for DMA channel 1.

I/O

Z

Functions: Input port 4, Output port 4, A27 input pin, general purpose

timer 0 output.

I/O

Z

Functions: Input port 5, Output port 5, A28 input pin, general purpose

timer 1 output.

I/O

Z

Functions: Input port 6, Output port 6, A29 input pin, end-of-process

indication for DMA channel 0.

I/O

Z

Functions: Input port 7, Output port 7, A30 input pin, end-of-process

indication for DMA channel 1.

Signal

CLK2

RESET

RSTOUT

EN5Vc

Clock, Reset and Configuration Signals

Type R

Description

I

2X clock input (in i960Jx/PPC401Gx systems, this signal is 2X the

processor frequency).

IS

RESET input.

O L RESET output from watchdog timer.

ISU

H

Selects 5V (driven high) or 3.3V (driven low) DRAM memory interface.

An internal weak pull-up is provided for backward compatibility.

Power and Ground Signals

Signal Type R

Description

VCC

-

POWER leads for CPU I/O and internal core logic. Connect to a 5V

board plane.

VCC3

-

POWER leads for DRAM interface signals. Connect to either a 5V or

3.3V board plane as determined by EN5V (5V only prior to revision B1).

GND

-

GROUND leads intended for external connection to a GND board plane.

a. R indicates state during reset.

b. Reset state is ’Z’ when 3.3V memory interface is selected via EN5V driven low. This feature can be used to

float the DRAM signals for board testing.

c. This signal was a no-connect prior to revision B1

Copyright © 1997, V3 Semiconductor Inc.

V96SSC Data Sheet Rev 2.3

11

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