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V96SSC-33LPREVB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

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V96SSC

2.7 Watchdog and System Heartbeat Timers

The V96SSC’s watchdog timer is used to recover a system that has crashed due to a software upset.

If the watchdog timer is not periodically reset by “trusted” system software, the V96SSC assumes that

a software crash has occurred and resets the processor by driving the RSTOUT pin low. The

V96SSC’s “system heartbeat” is a fixed-delay periodic interrupt to the processor that is used as a time

reference by real-time operating systems.

2.8 Bus Watch Timer (BWT)

Additional system security is provided by the Bus Watch Timer. When enabled, the BWT monitors the

READY pin (and, optionally, the PREADY pin) for every bus access initiated by an external master. If

READY is not asserted within a programmable window (between 1 and 255 clocks), then the V96SSC

will assert READY to end the cycle and generate an interrupt. For burst accesses, the BWT reloads its

time-out count on each READY and returns to idle on BLAST.

2.9 Interrupt Control Unit

The Interrupt Control Unit manages interrupts for all off the V96SSC’s on-chip interrupts, as well as

providing interrupt control for up to 8 external requests. Each pending request is latched in the

Interrupt Status Register. The Interrupt Mask Register allows independent masking of all interrupt

sources.

External interrupts may be routed to the Interrupt Control Unit via the I/O Multiplexer through the I/O

port unit.

2.10 I/O Port Unit

The I/O Port Unit provides 8 independent single bit input or output ports. Each bit may be configured

as an input port or an output port. As input ports, the unlatched inverted state of the associated pin is

read from the Input Port Register. In addition, the input port bits are connected to the Interrupt Control

Unit to provide external interrupt requests (IO[7:0] pins). When configured as an output port, the state

of the associated pin is set by writing to the Output Port Register.

The mapping of I/O Port bits to IOx pins is controlled via the I/O Multiplexer.

2.11 I/O Multiplexer

To allow the V96SSC to fit into a compact and economical 100-pin PQFP package, some non-

essential I/O signals are multiplexed onto the IO[15:0] pins. Many internal signals have several options

as to which IO pins they connect to. The multiplexing options for each IO pin are described in Table 4.

Programming of the I/O Multiplexer is described in the V96SSC User’s Manual.

2.12 Boot ROM Support

The V96SSC provides special support for boot ROM devices. When an access within the processor’s

boot range is detected on the A31, A[26:24] pins, the V96SSC outputs a latched low order address on

the MA[11:0] pins (normally the muxed address lines for DRAM) and asserts IOC0. The V96SSC

automatically detects boot ranges specific to each processor: 0x0000.0000 for the i960Sx,

0xFEFF.0000 for the i960Jx and 0xFFFF.0000 for PPC401Gx.

For i960Sx systems using 8-bit boot ROMs, the V96SSC will automatically steer the byte data to the

proper half of the AD bus (i960Jx processors handle byte assembly internally).

Copyright © 1997, V3 Semiconductor Inc.

V96SSC Data Sheet Rev 2.3

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