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V96SSC-33LPREVB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

needed. Eight output strobes/selects are available as output pins from the I/O Multiplexer.

There are eight memory decode registers, each with the following options:

• Base address and size (minimum granularity 64K)

• Region data width

• Read/Write enable

Each memory decode register has an associated Region Timing Control register. This register assigns

timings for synchronous mode strobes as well as for wait-state generation. The following timings are

programmable for each region:

• Strobe assert from bus cycle start

• Strobe de-assert from bus cycle start

• READY delay from cycle start (wait-states)

• Back-to-Back cycle delay

Each of the 8 chip select/strobe output pins is assigned to one of four programmable memory ranges.

These strobe signals can be used as asynchronous chip-selects, or combined with the timing values

for the region to create read and write strobes. Each strobe has the following programmable options:

• Address match register assignment

• Access type: read, write, both

• Timing: asynchronous, synchronous

• Sub-decode: finer granularity decoding

The chip select/strobe unit is also tied to the DMA Controller. Each DMA channel can be assigned to a

particular decode region and its associated timing.

2.6 General Purpose Timers (GPT)

Two identical 32-bit general purpose timers are integrated in the V96SSC. These timers may be used

for a number of applications including: periodic interrupt generation, event counting, and pulse width

modulation.

The timers decrement every clock cycle, from a 32-bit preload value until a terminal count of zero is

reached. A maskable interrupt is generated on terminal count. The timer may be programmed to halt

on terminal count, or to reload and restart counting.

Each timer has an external input (TIx) and external output pin (TOx). The TIx pin can be used as an

edge or level sensitive start trigger. The TOx pin has the following modes:

• Latched low

• Short and long pulse low on terminal count

• Toggle on terminal count

• Pulse width modulation

• One shot

6

V96SSC Data Sheet Rev 2.3

Copyright © 1997, V3 Semiconductor Inc.

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