V96SSC-33LPREVB1 Ver la hoja de datos (PDF) - QuickLogic Corporation

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V96SSC-33LPREVB1

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

Figure 1: V96SSC Block Diagram

A31,A[26:16]

AD[15:0]

BE[1:0]

ADS

ALE

BLAST

W/R

BTYPE[1:0]

HLDA

HOLD

INT

RESOUT

RESET

CLK2

i960

PROCESSOR

INTERFACE

BUS WATCH

SYSTEM

HEARTBEAT/

WATCHDOG

TIMERS

SERIAL

COMM

UNIT

DRAM

CONTROL

I/O

MUX

and

BIT I/O

TWO

CHANNEL

DMA

32-BIT

TIMERS (2)

CHIP SELECT

STROBE

LOGIC

V96SSC

MA[11:0]

RAS[1:0]

CAS[3:0]

WE

OE[1:0]

LE

I/O[15:0]

DREQ0

DACK0

DREQ1

DACK1

2.1 Direct i960 Sx/Jx and PPC401Gx Processors Bus Interface Units

The V96SSC is designed to connect directly to i960Sx/Jx and PPC401Gx processors. No “glue logic”

is required. Care was taken during the design of the V96SSC to insure full AC timing compatibility with

these processors running with bus speeds up to 33MHz. Even the pinout of the V96SSC has been

designed with ease of connection in mind.

At the beginning of each processor bus cycle the V96SSC samples the BTYPE[1:0] pins. As it’s shown

in the following table, these pins indicate what type of bus cycle is being run. Because the bus type is

dynamically detected, the V96SSC may be used in systems using both 16-bit and 32-bit masters.

BTYPE[1:0]

00

01

CPU Mode

i960SA/SB

PPC401Gx

Table 2: BTYPE[1:0] Pin Decoding

Boot Address

A[31, 26:24]=”0000”

A[31, 26:24]=”1111”

Description

16-bit data bus, BE[1:0] valid for current

cycle, both processor and V96SSC use 2x

clock

32-bit data bus, BE[3:0] valid for current

cycle, processor uses 1X clock and V96SSC

uses 2X clock

Copyright © 1997, V3 Semiconductor Inc.

V96SSC Data Sheet Rev 2.3

3

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