White Electronic Designs
WED9LC6816V
FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @
CAS LATENCY = 3, BURST LENGTH = 1
0
1
2
3
4
5
SDCK
tCC
tCH
tCL
SDCE#
tSS
SDRAS#
tRCD
tSH
SDCAS#
tSS
tSH
tSS
tSH
ADDR
Ra
Ca
6
7
8
9 10 11 12 13 14 15 16 17 18 19
tRAS
tRCD
tSS
tSH
tRP
tCCD
tSS
tSH
Cb
Cc
Rb
BA0, 1
BS
[A12,A13]
SDA10
Ra
DQ
SDWE#
BWE#
Row Active
BS
BS
BS BS
tRAC
tSAC
tSLZ
tSS
tSH
Qa
Db
tOH
tSS
tSH
tSS
tSH
BS
Rb
Qc
Read
Write
Read
Precharge
Row Active
DON’T CARE
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com