M32171F3VFP Ver la hoja de datos (PDF) - Renesas Electronics

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M32171F3VFP

32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

Renesas Electronics 

REVISION HISTORY

32171 Group User’s Manual

Rev. Date

Page

Description

Summary

1.0 Nov 1, 2002 P13-28 Figure 13.2.5 corrected

P13-29 Figure 13.2.6 corrected

P13-30 Figure 13.2.7 corrected

P13-35 Figure 13.2.8, “Relationship between Mask Registers and the Controlled Slots,” added

Figure 13.2.9, “ Operation of the Acceptance Filter,” added

P13-61 Explanation in (2) Confirming that transmission is idle corrected

P13-64 Figure 13.5.2 corrected

P13-65 Explanation in (2) Confirming that reception is idle corrected

P13-68 Figure 13.6.2 corrected

P13-71 Explanation in (2) Confirming that transmission is idle corrected

P13-75 Figure 13.7.2 corrected

P13-78 Explanation in (2) Confirming that reception is idle corrected

P13-82 Figure 13.8.2 corrected

P15-6 Figures 15.2.1 to 15.2.6 corrected (Address signals A12 to A30 and chip select signals

to P15-11 CS0, CS1 separately shown)

P15-12 Figures 15.3.1 and 15.3.2 corrected (Address signals A12 to A30 and chip select signals

to P15-13 CS0, CS1 separately shown)

P16-6 Figures 16.3.1 to 16.3.14 corrected (Address signals A12 to A30 and chip select signals

to P16-19 CS0, CS1 separately shown)

P18-2 Precautions added to Figure 18.1.1

P19-7 Figure 19.4.2 corrected

P19-14 Precautions added to Section 19.5, “Boundary Scan Description Language”

P19-14 BSDL description language for the 32171 (Figures 19.5.1 to 19.5.14) deleted

P19-15 Precautions added to Figure 19.6.1

P19-16 Precautions added to Section 19.7, “Processing Pins when Not Using JTAG”

Figure 19.7.1, “Processing Pins when Not Using JTAG,” added

P20-1 In Chapter 20, explanation of power supply turn-on/turn-off sequences during

to P20-16 VCCE=3.3V added

Chapter 20 overall, designations of “5V system” and “3.3V system” changed to “external

I/O” and “internal,” respectively

P20-12 Figure 20.3.6 corrected

P20-13 Figure 20.3.8, “CPU Reset State” deleted

P20-15 Figure 20.3.12, “SRAM Data Backup State” deleted

P21-3,

P21-4

Recommended operating conditions corrected (minimum value of analog reference

voltage added)

P21-5 (1) Electrical characteristics when f(XIN) = 10 MHz corrected

(4/8)

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