M32171F3VFP Ver la hoja de datos (PDF) - Renesas Electronics

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M32171F3VFP

32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

Renesas Electronics 

REVISION HISTORY

32171 Group User’s Manual

Rev. Date

Page

2.00 Sep 19, 2003 P5-17

Table 5.5.1 corrected

Description

Summary

P5-19,

P5-20

Description in (2) to (4), Section 5.5.2 changed

P5-21 Figure 5.5.2 changed

P6-43 Note 3 for Section 6.7.1 corrected

P6-44 Notes in Figures 6.7.2 and 6.7.3 corrected

P6-50 Figure, “Virtual-Flash Emulation Mode to Normal Mode Return Sequence” deleted

P7-1 to

P7-7

Chapter 7 overall,

The phrase “reset release” changed to “ exiting reset”

P7-3

Registers R0-R15 added to Table 7.3.1

P10-end Sections 10.7 to 10.9 deleted

P10-19, Note added

P10-20

P10-49 Figure 10.3.2, “Count Clock Dependent Delay”, newly added

P10-72 Figure (former 10.3.13), “Prescaler Delay”, deleted

P10-82 Figure 10.3.22 deleted

P10-83 to Section 10.4 overall,

P10-122 Description of DMA transfer request generation (for only the TIO8) newly added

P10-87 Description of “Count clock-dependent delay” along with Figure 10.4.2 newly added

P10-96 Figure 10.4.7, “Outline Diagram of TIO5-9 Clock/Enable Inputs”, altered

P10-103 Description of W= corrected

P10-115 (3), “Precautions on using TIO PWM output mode”, newly added

P10-119 Last item of Section 10.4.13. (2) added

P10-124 Figure 10.5.1 corrected

Description of “Count clock-dependent delay” along with Figure 10.5.2 newly added

P10-141 Second paragraph of Section 10.6.7. (1) corrected

P11-6 Description added to Section 11.1.2

P11-16 Note 1 added

P11-36

Conversion time for Comparator mode in Table 11.3.3 corrected

Incorrect: 27

Correct: 29

P11-39

“AD1CSTP” is deleted from the explanation of “Forcible termination during scan

operation” in Section 11.14

P11-41, Equations altered

P11-42

(6/8)

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