QL6325-E Ver la hoja de datos (PDF) - QuickLogic Corporation
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QL6325-E Datasheet PDF : 56 Pages
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QL6325E Eclipse-E Data Sheet Rev. F
NOTE: For PT280 and PS484 packages: All CLK, IOCTRL, and PLLIN pins are clamped to the VCCIO(C)
rail. Therefore, these pins can be driven up to VCCIO(C). All JTAG inputs are clamped to the VDED2
rail. These JTAG input pins can only be driven up to VDED2.
Figure 16 through Figure 19 show the VIL and VIH characteristics for I/O and clock pins.
Figure 16: VIL Maximum for I/O
VILmax for IO
2.5
2
1.5
1
0.5
0
-55C -40C
0C 25C 70C 90C 110C 125C
Junction Temperature
1.71 V
1.8 V
1.89 V
2.5 V
3.3 V
3.6 V
Figure 17: VIH Minimum for I/O
VIHmin for IO
2.5
2
1.5
1
0.5
0
-55C -40C 0C 25C 70C 90C 110C 125C
Junction Temperature
1.71 V
1.8 V
1.89 V
2.5 V
3.3 V
3.6 V
20
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