QL6325-E Ver la hoja de datos (PDF) - QuickLogic Corporation

Número de pieza

componentes Descripción

Fabricante

QL6325-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

QL6325E Eclipse-E Data Sheet Rev. F

Figure 15: Required Power-Up Sequence When Using Power-Up Loading

VCCIO

VDED

VDED2

VPUMP

VCC

VCC PLL

VCC

< 2 ms

Time

To use the power-up loading function, designers must ensure that VCC begins to ramp within a maximum of

2 ms of VCCIO, VDED, VDED2, and VPUMP.

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