QL6325-E Ver la hoja de datos (PDF) - QuickLogic Corporation
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QL6325-E Datasheet PDF : 56 Pages
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QL6325E Eclipse-E Data Sheet Rev. F
Table 11: DC Characteristics
Symbol
II
IOZ
CI
CCLOCK
Parameter
I or I/O Input Leakage Current
3-State Output Leakage Current
I/O Input Capacitancea
Clock Input Capacitance
IOS
Output Short Circuit Currentb
IDED D.C. Supply Current on VDED
IREF D.C. Supply Current on INREF
IPD Current on programmable pull-down
ICCIO D.C. Supply Current on VCCIO
IPUMP
IPLL
ICC
D.C. Supply Current on VPUMP
D.C. Supply Current on each VCCPLL
D.C. Supply Currentc, d
Conditions
VI = VCCIO or GND
VI = VCCIO or GND
-
-
VO = GND
VO = VCC
-
-
VCC = 1.8 V
VCCIO = 1.8 V
VCCIO = 2.5 V
VCCIO = 3.3 V
VPUMP = 3.3 V
2.5 V
VPUMP = 0 V
VPUMP = 3.3 V
Min
Max
Units
-10
10
µA
-
10
µA
-
8
pF
-
8
pF
-15
-180
mA
40
210
mA
-
-
µA
-10
10
µA
-
50
µA
10
-
10
µA
20
-
-
µA
-
3
mA
-
10
mA
-
-
mA
a. Capacitance is sample tested only. Clock pins are 12 pF maximum.
b. Only one output at a time. Duration should not exceed 30 seconds.
c. For -6/-7/-8 commercial grade devices only. Maximum ICC is 15 mA for all industrial grade devices and 25 mA for all
military devices.
d. ICC is for current drawn by VCC and VDED. If any PLLs are used, see Table 11 for current drawn by each PLL.
Table 12: DC Input and Output Levelsa
INREF
VIL
VIH
VOL
VOH
IOL IOH
VMIN VMAX VMIN
VMAX
VMIN
VMAX
VMAX
VMIN
mA mA
LVTTL n/a n/a -0.3
0.8
2.2
VCCIO + 0.3
0.4
2.4
2.0 -2.0
LVCMOS2 n/a n/a -0.3
0.7
1.7
VCCIO + 0.3
0.7
1.7
2.0 -2.0
LVCMOS18 n/a n/a -0.3
0.63
1.2
VCCIO + 0.3
0.7
1.7
2.0 -2.0
GTL+ 0.88 1.12 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3
0.6
n/a
40 n/a
PCI
n/a n/a -0.3 0.3 x VCCIO 0.6 x VCCIO VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5
SSTL2 1.15 1.35 -0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3
0.74
1.76 7.6 -7.6
SSTL3 1.3 1.7 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3
1.10
1.90
8 -8
a. The data provided in Table 12 are JEDEC and PCI specifications—QuickLogic devices either meet or exceed
these requirements. For data specific to QuickLogic I/Os, see Table 17 through Table 22 and Figure 34 through
Figure 38.
NOTE: For PQ208 package: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore,
these pins can be driven up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG
input pins can only be driven up to VDED2.
© 2005 QuickLogic Corporation
www.quicklogic.com
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