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CX11250

SmartHSF™ Mobile Modem

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SmartHSF Mobile Modem Data Sheet

4.1.19 0x42 - PMC - Power Management Capabilities

The HSD contains power management as described in the PCI Power Management Specification, Revision 1.0 Draft, dated

Mar 18, 1997.

The HSD Configuration registers include the following Power Management features:

• Status register bit 4 set to 1 to indicate support for New Capabilities

• Capabilities Pointer (CAP_PTR) at offset 0x34 containing hardcoded value 0x40

• Power Management Register block at offset 0x40 and 0x44 (see Table 4-1)

The Power Management Capabilities register is a 16-bit read-only register which provides information on the capabilities of

the function related to power management (Table 4-4).

Bit

2:0

3

4

5

8:6

9

10

15:11

Table 4-4. Power Management Capabilities (PMC) Register

R/W

Description

R

Version. 010b indicates compliance with Revision 1.0 of the PCI Power Management Interface

Specification.

R

PME Clock. Hard coded to 0 to indicate that the PCI clock is not required for PME generation.

R

Reserved (= 0).

R

DSI (Device Specific Initialization). Loaded from serial EEPROM.

R

Aux. Current. Loaded from serial EEPROM.

R

D1_Support. When set to a 1, the HSD device supports D1 power state (loaded from serial EEPROM).

R

D2_ Support. When set to a 1, the HSD device supports D2 power state (loaded from serial EEPROM).

R

These 5 bits indicate which power states allow assertion of PME (loaded from serial EEPROM). A value of

0 for any bit indicates that the function cannot assert the PME# signal while in that power state.

Bit 11: 1 = PME# can be asserted from D0

Bit 12: 1 = PME# can be asserted from D1

Bit 13: 1 = PME# can be asserted from D2

Bit 14: 1 = PME# can be asserted from D3hot

Bit 15: 1 = PME# can be asserted from D3cold.

4.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4)

This 16-bit register is used to manage the PCI function’s power management state as well as to enable/monitor power

management events (Table 4-5).

Table 4-5. Power Management Control/Status Register (PMCSR)

Bit

R/W

Description

1:0

R/W Power State.

00 = D0

01 = D1

10 = D2

11 = D3.

7:2

R

Reserved (= 000000b).

8

R/W PME_En. A 1 enables PME assertion.

12:9

R/W Data_Select. Selects Data and Data Scale fields.

14:13

R

Data Scale. Associated with Data field. Loaded from serial EEPROM.

15:11

R/C PME_Status. This bit is sticky when PME assertion from D3_cold is supported.

PME_Status = 1 indicates PME asserted by the HSD device. Writing 1 clears PME_Status. Writing 0 has

no effect.

R: Bit(s) is (are) read only.

R/W: Bit(s) is (are) readable and writeable.

R/C: Bit(s) is (are) readable, and clearable by writing 1 (bit may not be set by writing).

100553B

Conexant

4-5

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