ADF7020BCPZ Ver la hoja de datos (PDF) - Analog Devices

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ADF7020BCPZ

High Performance, ISM Band, FSK/ASK Transceiver IC

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF7020

VCOIN 1

CREG1 2

VDD1 3

RFOUT 4

RFGND 5

RFIN 6

RFINB 7

RLNA 8

VDD4 9

RSET 10

CREG4 11

GND4 12

ADF7020

TOP VIEW

(Not to Scale)

36 CLKOUT

35 DATA CLK

34 DATA I/O

33 INT/LOCK

32 VDD2

31 CREG2

30 ADCIN

29 GND2

28 SCLK

27 SREAD

26 SDATA

25 SLE

NOTES

1. EXPOSED PAD MUST BE CONNECTED TO GROUND.

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic

Description

1

VCOIN

The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).

The higher the tuning voltage, the higher the output frequency.

2

CREG1

Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this

pin and ground for regulator stability and noise rejection.

3

VDD1

Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as

possible to this pin. All VDD pins should be tied together.

4

RFOUT

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The

output should be impedance matched to the desired load using suitable components. See the Transmitter

section.

5

RFGND

Ground for Output Stage of Transmitter. All GND pins should be tied together.

6

RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. See the LNA/PA Matching section.

7

RFINB

Complementary LNA Input. See the LNA/PA Matching section.

8

RLNA

9

VDD4

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.

10

RSET

External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5%

tolerance.

11

CREG4

Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND

for regulator stability and noise rejection.

12

GND4

Ground for LNA/MIXER Block.

13 to 18

MIX_I, MIX_I,

MIX_Q, MIX_Q,

FILT_I, FILT_I

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

19, 22

GND4

Ground for LNA/MIXER Block.

20, 21, 23 FILT_Q, FILT_Q,

TEST_A

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

24

CE

Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when

CE is low, and the part must be reprogrammed once CE is brought high.

25

SLE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the fourteen latches. A latch is selected using the control bits.

26

SDATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high

impedance CMOS input.

Rev. D | Page 11 of 48

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