ADF7020BCPZ Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

ADF7020BCPZ

High Performance, ISM Band, FSK/ASK Transceiver IC

Analog Devices 

ADF7020

Pin No.

27

28

29

30

31

32

33

Mnemonic

SREAD

SCLK

GND2

ADCIN

CREG2

VDD2

INT/LOCK

34

DATA I/O

35

DATA CLK

36

CLKOUT

37

MUXOUT

38

39

40

41

42

43

44 to 47

48

OSC2

OSC1

VDD3

CREG3

CPOUT

VDD

GND, GND1,

VCO GND

CVCO

EP

Data Sheet

Description

Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The

SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Ground for Digital Section.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V

to 1.9 V. Readback is made using the SREAD pin.

Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between

this pin and ground for regulator stability and noise rejection.

Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to

this pin.

Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has

found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to

lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked,

NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay.

Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.

In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the

center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data

from the microcontroller into the transmit section at the exact required data rate. See the Gaussian

Frequency Shift Keying (GFSK) section.

A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be

used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-

space ratio.

This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct

frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface

regulator.

The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by

driving this pin with CMOS levels and disabling the crystal oscillator.

The reference crystal should be connected between this pin and OSC2.

Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a

0.01 µF capacitor.

Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be

placed between this pin and ground for regulator stability and noise rejection.

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.

Grounds for VCO Block.

A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.

Exposed Pad. The exposed pad must be connected to ground.

Rev. D | Page 12 of 48

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