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73K222AU Ver la hoja de datos (PDF) - TDK Corporation

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73K222AU
TDK
TDK Corporation TDK
73K222AU Datasheet PDF : 40 Pages
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73K222AU
Single-Chip Modem
with UART
UART CONTROL REGISTER OVERVIEW
REGISTER
RECEIVER
BUFFER
REGISTER
(READ ONLY)
TRANSMIT
HOLDING
REGISTER
(WRITE ONLY)
RBR
THR
INTERRUPT
ENABLE
IER
REGISTER
INTERRUPT
ID
REGISTER
IIR
(READ ONLY)
LINE
CONTROL
REGISTER
LCR
UART
ADDRESS
UA3-UA0*
0000
DLAB = 0
0000
DLAB = 0
0001
DLAB = 0
0010
0011
MODEM
CONTROL
REGISTER
MCR
0100
LINE
STATUS
REGISTER
MODEM
STATUS
REGISTER
(READ ONLY)
LSR
MSR
0101
0110
SCRATCH
REGISTER
SCR
0111
D7
BIT 7
(MSB)
BIT 7
(MSB)
0
0
DIVISOR
LATCH
ACCESS
(DLAB)
0
0
DATA
CARRIER
DETECT
(DCD)
BIT 7
DATA BIT NUMBER
D6
D5
D4
D3
D2
D1
D0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ENABLE
0
0
8250A/
16C450
INTERRUPT
0
0
0
SET
BREAK
STICK
PARITY
EVEN
PARITY
SELECT
(EPS)
0
0
LOOP
TRANSMIT
SHIFT REG
EMPTY
(TSRE)
TRANSMIT
HOLDING
REGISTER
EMPTY(THRE)
BREAK
INTERRUPT
(BI)
RING
INDICATOR
(RI)
DATA
SET READY
(DSR)
CLEAR
TO SEND
(CTS)
ENABLE
MODEM
STATUS
INTERRUPT
0
PARITY
ENABLE
(PEN)
ENABLE
INTERRUPT
(OUT2 IN
16C450)
FRAMING
ERROR
(FE)
DELTA
DATA CARR.
DETECT
(DDCD)
ENABLE
REC. LINE
STATUS
INTERRUPT
INTERRUPT
ID
BIT 1
NUMBER
OF STOP
BITS
(STB)
PRST
(OUT1 IN
16C450)
PARITY
ERROR
(PE)
TRAILING
EDGE RING
INDICATOR
(TERI)
ENABLE
THR
EMPTY
INTERRUPT
INTERRUPT
ID
BIT 0
WORD
LENGTH
SELECT 1
(WLS1)
REQUEST
TO SEND
(RTS)
OVERRUN
ERROR
(OE)
DELTA
DATA SET
READY
(DDSR)
ENABLE
REC. DATA
AVAILABLE
INTERRUPT
"0" IF
INTERRUPT
PENDING
WORD
LENGTH
SELECT 0
(WLS0)
DATA
TERMINAL
READY
(DTR)
DATA
READY
(DR)
DELTA
CLEAR
TO SEND
(DCTS)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIVISOR
LATCH
(LS)
DLL
0000
DLAB = 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
DIVISOR
LATCH
(MS)
DLM
0001
DLAB = 1
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
* In single-port mode (STNDLN pin = 1), all four address lines UA3-UA0 are used to address the UART Control Registers.
* In dual-port mode (STNDLN pin = 0), only three address lines UA2-UA0 are used to address the UART Control Registers,
the UA3 pin becomes the MA2 pin in this mode.
BIT 1
BIT 9
BIT 0
BIT 8
11

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