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73K222AU

Single-Chip Modem Modem with UART

TDK Corporation 

73K222AU

Single-Chip Modem

with UART

MODEM STATUS REGISTER (MSR) (READ ONLY)

STNDLN:

0

1

ADDRESS:

UA2 - UA0 = 110

UA3 - UA0 = 0110

UART SECTION

This register provides the current state of the control signals from the modem. In addition, four bits provide

change information. The CTS, DSR, DCD, and RI signals come from the UART Control Register if

STNDLN = 0 and from the CTS, DSR, DCD and RI pins (inverted) if STNDLN = 1. This register is READ ONLY.

The delta bits indicate whether the inputs have changed since the last time the Modem Status Register has been

read. In Loop Mode CTS, DSR, RI and DCD are taken from RTS, DTR, µPRST, and Enable Interrupt in the

Modem Control Register respectively.

BIT NO.

D0

D1

D2

D3

D4

D5

D6

D7

NAME

DCTS

DDSR

TERI

DDCD

CTS

DSR

RI

DCD

CONDITION

1

1

1

1

1

1

1

1

DESCRIPTION

This bit is the Delta Clear to Send (DCTS) indicator. Bit

0 indicates that the CTS input to the chip has changed

state since the last time it was read by the CPU.

This bit is the Delta Data Set Ready (DDSR) indicator.

Bit 1 indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU.

This bit is the Trailing Edge of the Ring Indicator (TERI)

detector. Bit 2 indicates that the RI input to the chip has

changed state.

This bit is the Delta Data Carrier Detect (DDCD)

indicator. Bit 3 indicates that the DCD input to the chip

has changed state.

This bit is the complement of the Clear To Send (CTS)

input. If STNDLN = 0, this reflects the status of the

UART Control Register bit. If bit 4 (loop) of the MCR is

set to a 1, this bit is equivalent to RTS in the MCR.

This bit is the complement of the Data Set Ready (DSR)

input. If STNDLN = 0, this reflects the status of the

UART Control Register bit. If bit 4 of the MCR is set to a

1, this bit is the equivalent of DTR in the MCR.

This bit is the complement of the Ring Indicator (RI)

input. If STNDLN = 0, this reflects the status of the

UART Control Register bit. If bit 4 of the MCR is set to a

1, this bit is equivalent to µPRST in the MCR.

This bit is the complement of the Data Carrier Detect

(DCD) If STNDLN = 0, this reflects the status of the

UART Control Register bit. If bit 4 of the MCR is set to a

1, this bit is equivalent to Enable Interrupt in the MCR.

19

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