EP2AGZ300HH40I5ES Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

EP2AGZ300HH40I5ES

Arria II Device Handbook

Unspecified 

1–6

Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Arria II Device Architecture

Arria II devices include a customer-defined feature set optimized for cost-sensitive

applications and offer a wide range of density, memory, embedded multiplier, I/O,

and packaging options. Arria II devices support external memory interfaces and I/O

protocols required by wireless, wireline, broadcast, computer, storage, and military

markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and

high-performance DSP blocks from the Stratix® IV device family with a

cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.

Figure 1–1 and Figure 1–2 show an overview of the Arria II GX and Arria II GZ device

architecture, respectively.

Figure 1–1. Architecture Overview for Arria II GX Devices

DLL

High-Speed Differential I/O,

High-Speed Differential I/O,

General Purpose I/O, and

General Purpose I/O, and

PLL

PLL

Memory Interface

Memory Interface

Transceiver

Blocks

Arria II GX FPGA Fabric

(Logic Elements, DSP,

Embedded Memory, Clock Networks)

All the blocks in this graphic are for the largest density in the

Arria II GX family. The number of blocks can vary based on

the density of the device.

Plug and Play PCIe hard IP

×1,×2, ×4, and ×8

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

PLL

PLL

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

High-Speed Differential I/O,

PLL

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

PLL

DLL

Arria II Device Handbook Volume 1: Device Interfaces and Integration

July 2012 Altera Corporation

Share Link: