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EP2AGZ300HH40I5ES

Arria II Device Handbook

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1–4

Chapter 1: Overview for the Arria II Device Family

Arria II Device Feature

Table 1–2 and Table 1–3 list the Arria II device package options and user I/O pin

counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra

FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.

Table 1–2. Package Options and I/O Information for Arria II GX Devices (Note 1), (2), (3), (4), (5), (6), (7)

Device

358-Pin Flip Chip UBGA 572-Pin Flip Chip FBGA

17 mm x 17 mm

25 mm x 25 mm

780-Pin Flip Chip FBGA

29 mm x 29 mm

1152-Pin Flip Chip FBGA

35 mm x 35 mm

I/O LVDS (8)

I/O LVDS (8)

I/O LVDS (8)

I/O LVDS (8)

EP2AGX45

33(RD or eTX)

156 + 32(RX, TX,

or eTX)

4

57(RD or

252

eTX) +

56(RX, TX,

or eTX)

85(RD or eTX)

8 364 + 84(RX, TX, 8

or eTX)

—

—

—

EP2AGX65

33(RD or eTX)

156 + 32(RX, TX,

or eTX)

4

57(RD or

252

eTX) +

56(RX, TX,

or eTX)

85(RD or eTX)

8 364 +84(RX,TX, 8

eTX)

—

—

—

EP2AGX95 —

—

57(RD or

—

260

eTX) +

56(RX, TX,

or eTX)

8

85(RD or eTX)

372 +84(RX, TX, or

eTX)

12

105(RD or

452

eTX) +

104(RX, TX, or

eTX)

12

EP2AGX125 —

—

57(RD or

—

260

eTX) +

56(RX,TX, or

eTX)

8

85(RD or eTX)

372 +84(RX,TX, or

eTX)

12

105(RD or

452

eTX) +

104(RX, TX, or

eTX)

12

EP2AGX190 —

—

——

—

—

85(RD or eTX)

372 +84(RX, TX, or

eTX)

12

145(RD or

612

eTX) +

144(RX, TX, or

eTX)

16

85(RD, eTX)

145(RD, eTX) +

EP2AGX260 —

—

——

—

— 372 +84(RX, TX, or 12 612 144(RX, TX, or 16

eTX)

eTX)

Notes to Table 1–2:

(1) The user I/O counts include clock pins.

(2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,

and power pins are the same for a given package across device densities.

(3) RD = True LVDS input buffers with on-chip differential termination (RD OCT) support.

(4) RX = True LVDS input buffers without RD OCT support.

(5) TX = True LVDS output buffers.

(6) eTX = Emulated-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.

(7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.

(8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks.

Arria II Device Handbook Volume 1: Device Interfaces and Integration

July 2012 Altera Corporation

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