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MT90737AM

CMOS DS3/DS1 MUX/DEMUX (M13)

Mitel Networks 

MT90737 CMOS

Preliminary Information

Functional Description

The MT90737 (M13) multiplexes and demultiplexes 28

DS1 signals to and from a DS3 signal in either M13 or

C-bit parity mode. In the C-bit parity mode, the

MT90737 provides a separate transmit (13 bits) and

receives (14 bits) interface for C-bits. The Far End

Alarm and Control (FEAC) channel (C3) is accessed

via internal memory. The MT90737 has 37 byte regis-

ters for software control, performance counters, and

alarm reporting. The microprocessor interface is

selectable via two external hardware straps. Interface

options are Multiplexed and Non-Multiplexed bus types

(such as Intel 80X86 and Motorola 680X0 families).

The MT90737 supports Bellcore’s TR-TSY-000499,

ANSI’s T1.107-1988 and supplement T1.107a-1990.

Figure 1 shows a functional block diagram of the

MT90737.

Multiplex (Transmit)

In the transmit direction, DS1 transmit data (DTn) is

clocked into the MT90737 on positive transitions of the

clock input (CTn) for each of the 28 DS1 channels. A

DS1 Input Block, which consists of a FIFO and sup-

porting logic, is provided for each DS1 channel. Under

software control, the MT90737 can invert the transmit

data signals, or the clock signals for all 28 DS1 chan-

nels. The data inversion feature provides compatibility

with certain T1 line interface devices, while the clock

inversion feature allows back-to-back M13 operation.

The DS1 Input Block is also used to insert one of three

available idle patterns from a common generator into a

DS1 bit stream, under software control. The selection

of the idle pattern is common to all 28 DS1 channels.

The idle patterns are: a Quasi-Random Sequence

(QRS), an Extended Super Frame DS1 (ESF) format

with all ones in channels one through 24, and an AIS

format (unframed all ones).

Each DS1 signal is bit-multiplexed into the respective

DS2 frame, with the stuff bits inserted based on the fill

level of an internal FIFO. When the level of the FIFO

drops below half full, a stuff bit is inserted into the DS1

bit stream in the DS2 signal. The DS2 signal is formed

by combining four DS1 signals. In each DS2 frame

there are 287 data bit positions per DS1 channel, one

stuff bit per DS1 channel and 24 overhead bits for a

total of 1176 bits. The overhead bits are used for fram-

ing, X-bit channel and stuff control.

The DS3 signal is partitioned into M-frames of 4760

bits each. The M-frames are divided into seven M-sub-

frames having 680 bits each. Each M-subframe is fur-

ther divided into eight blocks of 85 bits each. Each

block uses 84 bits for payload and one bit for frame

overhead. There are 56 overhead bits in each M-

frame. the M-frame alignment uses three bits, the M-

subframe alignment (F-bits) uses 28 bits, 21 bits are

defined as C-bits, two bits are assigned for parity, and

two bits are assigned for the X-bit channel.

The DS3 frame is constructed and timed according to

the operating mode, i.e., C-bit parity mode or M13

mode.

C-Bit Parity Mode

In the C-bit parity mode, all seven of the DS2 stuff bits

are fixed as stuff, resulting in 7 pseudo DS2 frames of

671 bits per DS2 frame in each DS3 frame, for a DS2

rate of 6.3062723 Mbit/s. Since stuffing always occurs,

the 21 C-bits are assigned for other functions, as

shown in Figure 2. A C-bit interface is provided for

transmitting 13 C-bits (C2, C4, C5, C6, C13, C14, C15,

C16, C17, C18, C19, C20, C21). The external transmit

C-bit interface consists of a serial data input (CDT), an

output clock (CCKT), a data link indicator pulse

(CDCCT), and an output framing pulse (CFMT). The

data link indicator pulse identifies the location of the

three data link bits, C13, C14, and C15. In addition, a

control bit (C3CLKI) is provided in the memory map

(register 19H) which enables the MT90737 to gener-

ate an extra clock cycle in CCKT during the C3 bit

time.

Of the eight remaining C-bits, C1 is used as an identifi-

cation channel; C3 is defined as a Far End Alarm and

Control (FEAC) bit; C7, C8, and C9 (CP-bits) are used

for C-bit parity; and the remaining three bits, C10, C11,

and C12, are used to transmit a Far End Block Error

(FEBE) indication. C1 should be set to 1 under C-bit

parity mode. The FEAC channel carries alarm or sta-

tus information from the far-end terminal to the near-

end terminal, and is also used to initiate DS3 and DS1

loopbacks at the far-end terminal from the near-end

terminal. The CP-bits are used to carry DS3-path par-

ity information for end-to-end parity checking. Since

the CP-bits pass through the network unchanged

(except in the case of an AIS or CP-bit errors), the DS3

receiver can determine if an error has occurred in an

M-frame by computing the contents of the given M-

frame and comparing this parity value with the parity

received in the CP-bits in the following M-frame. If a

received C-bit parity error or framing error is detected,

the FEBE bits shall be returned to the transmitting ter-

minal to indicate the error occurrence. Thus, the over-

all performance of the full-duplex DS3 path, under C-

bit parity mode, can be determined at either end or at

any place along the path with the FEAC and FEBE sig-

nals.

5-72

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