MT90737AM Ver la hoja de datos (PDF) - Mitel Networks
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MT90737AM Datasheet PDF : 40 Pages
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Preliminary Information
CMOS MT90737
Control Bits
Pin #
Name I/O/P
Description
164
OUTDIS
I Outputs Disable. TTL Type II compatible. A low causes all MT90737 outputs
and bi-directional signal leads to be set to a high impedance state for test pur-
poses except the CDCCR and CDCCT pins. The CDCCR and CDCCT outputs
are controlled by DLEN pin. OUTDIS is provided with an internal pull-up resis-
tor.
204
DLEN
I Data Link Enable. TTL Type II compatible. Normally left open. A high enables
the transmit and receive data link indication signals, CDCCT and CDCCR. The
data link indication signals identify the location of the three data link C-bits
(C13, C14, and C15). A low puts CDCCR and CDCCT into high impedance
state.
144
TEST
O Test Pin. Leave open.
Note: I = Input; O = Output; P = Power. See DC Characteristics section for CMOS and TTL Type definitions.
External Clock
Pin #
Name I/O/P
Description
90
XCK
I External Transmit Clock. CMOS compatible. An external clock having a fre-
quency of 44.736 MHz ±20 ppm is required to meet DSX-3 cross-connect
requirements. The clock duty cycle should be 50 ±5%. The transmit clock is
also used to operate the microprocessor interface. The MT90737 monitors this
clock for transitions. When a clock failure is detected, the MT90737 automati-
cally switches to the receive clock (DS3CR) for multiplexer and microproces-
sor operation. Receive loop timing (a one written to bit 3, LPTIME, in 02H) also
causes the receive clock to become the transmit clock.
Note: I = Input; O = Output; P = Power. See DC Characteristics section for CMOS and TTL Type definitions.
Boundary Scan Pins
Pin #
Name I/O/P
Description
148
TBMS
I Test Boundary Mode Select. TTL Type II compatible. The signal present on
this lead is clocked in by the positive transitions of TBCK to control test opera-
tions.
149
TBDI
I Test Boundary Data Input. TTL Type II compatible. Serial data input clocked
in by positive transitions of TBCK as boundary scan test messages.
150
TBDO
O Test Boundary Data Output. TTL Type IV compatible. Serial data output
whose information is clocked out on negative transitions of TBCK. A pull-up
resistor is required for this tri-stating pin.
151
TBCK
I Test Boundary Scan Clock. TTL Type II compatible.The input clock for
boundary scan testing.
152
TRS
I Test Boundary Scan Reset. TTL Type II compatible. When a low signal is
applied to this pin, the MT90737 Test Access Port (TAP) controller resets and
the boundary scan is disabled. The TAP is also reset upon power-up or by
holding the TBMS signal lead high for at least five rising clock transitions of
TBCK. When the boundary scan feature is not used, TRS must be held low.
Note: I = Input; O = Output; P = Power. See DC Characteristics section for CMOS and TTL Type definitions.
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