WED3C7558M-XBX Ver la hoja de datos (PDF) - White Electronic Designs Corporation
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WED3C7558M-XBX Datasheet PDF : 13 Pages
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White Electronic Designs
WED3C7558M-XBX
POWER CONSUMPTION
VCC = AVCC = 2.0 ± 0.1V Vdc, OVCC = 3.3V ± 5% Vdc, GND = 0 Vdc, 0 ≤ TJ < 105°C
Processor (CPU) Frequency/L2 Frequency
Full-on Mode
Doze Mode
Nap Mode
Sleep Mode
Sleep Mode–PLL and DLL Disabled
Typical
Maximum
Maximum
Maximum
Maximum
Maximum
300/150 MHz
4.1
6.7
2.5
1700
1200
500
350/175MHz
4.6
7.9
2.8
1800
1300
500
Unit Notes
W
1, 3
W
1, 2
W
1, 2
mW
1, 2
mW
1, 2
mW
1, 2
NOTES:
1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system dependent, but is typically
<10% of VCC power. Worst case power consumption, for AVCC=15mW and L2AVCC=15mW.
2. Maximum power is measured at VCC=2.1V while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally busy.
3. Typical power is an average value measured at VCC=AVCC=L2AVCC=2.0V, OVCC=L2OVCC=3.3V in a system, executing typical applications and benchmark sequences.
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure
and operate the L2 cache. It is cleared by hard reset or power-on reset.
FIGURE 5 – L2 CACHE CONTROL REGISTER (L2CR)
L2PE
L2WT
L2DO L2CTL L2TS
L2DF
L2SL L2BYP
L2CS
L2IO L2DRO
L2IP
L2E L2SIZ L2CLK L2RAM L2I
L20H
00
01 2 3 4
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
The L2CR bits are described in Table 1.
L2CTR
30 31
Reserved
August 2002
Rev. 7
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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