UPD63335 Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD63335

STEREO SOUND CODEC

NEC => Renesas Technology 

µ PD63335

(2) When using the slave mode (LRCLK, BIT_CLK supplied from external)

(a) To start ADC, DAC operation from the ADC, DAC power down status (including at power ON)

<1> Set the DAC volume register (10h, 11h) and DAC master volume register (14h, 15h) to MUTENote 1.

<2> Start supplying the external clock (LRCLK, BIT_CLK)Note 2.

<3> Set the LRCLK/BIT_CLK operation mode (use the reset/clock status register (00h)).

<4> Set the audio format (use the interface/timing register (01h)).

<5> Cancel ADC, DAC power down (use the power down control register (18h)).

<6> Set the DAC volume register (10h, 11h) and the DAC master volume register (14h, 15h)Note 3.

(b) To change the LRCLK/BIT_CLK operation mode setting during ADC, DAC operation

<1> Set the DAC volume register (10h, 11h) and the DAC master volume register (14h, 15h) to MUTENote 4.

<2> Switch the external clock (LRCLK, BIT_CLK)Note 5.

<3> Change the LRCLK/BIT_CLK operation mode setting (use the reset/clock status register (00h)).

<4> Set the audio format (if there is a change) (use the interface/timing register (01h)).

<5> Set the DAC volume register (10h, 11h) and the DAC master volume register (14h, 15h)Note 6.

Notes 1. Immediately after canceling ADC, DAC power down, noise may occur in the ADC and DAC

outputs. For this reason, before canceling power down, set the volume for DAC output to

MUTE. (If these volumes are already set to MUTE, at power ON, etc., setting them to MUTE

again is not required.)

2. Start supplying the external clock (LRCLK, BIT_CLK) prior to setting the LRCLK/BIT_CLK

operation mode.

3. To prevent popping noises, after canceling power down and following the lapse of an interval of

time sufficient for three or more LRCLK cycles to be supplied, cancel the MUTE setting of the

volume for the DAC output. Also handle the ADC output data (SO) as valid data once the same

interval of time has elapsed.

4. Immediately after changing the LRCLK/BIT_CLK operation mode, noise may occur in the ADC

and DAC outputs. For this reason, before changing this setting, set the volume for DAC output

to MUTE.

5. Start supplying the external clock (LRCLK, BIT_CLK) immediately it has been changed prior to

changing the LRCLK/BIT_CLK operation mode setting.

6. To prevent popping noises, after changing the LRCLK/BIT_CLK operation mode, following the

lapse of an interval of time sufficient for three or more LRCLK cycles to be supplied, cancel the

MUTE setting of the volume for the DAC output. Also handle the ADC output data (SO) as valid

data once the same interval of time has elapsed.

14

Data Sheet S15003EJ6V0DS

Share Link: