UPD63335 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD63335 Datasheet PDF : 56 Pages
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µ PD63335
1.6.2 Serial data interface
Four sampling frequency settings can be made for the µPD63335 by setting the RATE[1:0] bit in an internal
register (00h). Registers 00h and 01h can be used to set the polarity of the frame signal (LRCLK) and to switch the
I/O status of the LRCLK and BIT_CLK signals. Some noise may occur when switching the format of the serial data
interface during operation. Before switching, set the analog output volume to “mute” (see 2.1.14 to 2.1.16).
Selection of sampling rate (set via RATE[1:0] bit in register 00h)
RATE [1:0]
00
01
10
11
Sampling Rate
fMCLK/3072 (initial value)
fMCLK/1536
fMCLK/768
fMCLK/512
In Case of fMCLK = 24.576 MHz
8 kHz
16 kHz
32 kHz
48 kHz
Selection of audio data format (set via FSDF[2:0] bit in register 01h)
FSDS [2:0]
000
001
010
011
100
101
110
111
Bit Clocks per Frame
64
64
64
64
48
48
48
32 (initial value)
Audio Data Format (2’s Complement, MSB First)
PCM Input Data: SI
PCM Output: SO
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−
−
Selection of LRCLK polarity (set via LRCLKS bit in register 00h)
LRCLKS
0
1
LRCLK Level
High Level
Low Level
L channel (initial value)
R channel (initial value)
R channel
L channel
Selection of LRCLK/BIT_CLK direction (set via CLKIOS bit in register 00h)
CLKIOS
0
1
LRCLK/BIT_CLK Direction
Input (initial value)
Output
The µPD63335 can operate in both master mode (the mode in which the µPD63335 outputs LRCLK and
BIT_CLK) and slave mode (the mode in which the µPD63335 is supplied with LRCLK and BIT_CLK externally). Set
the registers related to each mode using the recommended procedure below.
12
Data Sheet S15003EJ6V0DS
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