UPD16704P Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD16704P

240-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µ PD16704

4. TIMING CHART (R,/L = H)

As shown in the figure below, when DS = H, scan signals are output successively from two outputs in synchronization

with the rise of CLK (double scan operation).

It is also possible to accelerate the fall timing of one of the scan signals (the output side in normal scan mode) in a

double scan operation by using the DSOE signal. DSOE is input asynchronously to the clock, and the output is fixed to

VEE2 in the period between the rise of DSOE and the rise of CLK.

The DSOE signal is only enabled during a double scan operation.

CLK

OE

DS

DSOE

STV

O1

O2

O3

O4

O5

O6

O7

Data Sheet S15809EJ1V0DS

9

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