HSP45314 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HSP45314

CommLink™ Direct Digital Synthesizer

Intersil 

HSP45314

necessity to have a 50Ω impedance looking back into the

transformer is negated if the DDS is only driving a short

trace. The output voltage compliance range does limit the

impedance that is loading the DDS output.

Ground Plane Considerations

Separate digital and analog ground planes should be used.

All of the digital functions of the device and their

corresponding components should be located over the

digital ground plane and terminated to the digital ground

plane. The same is true for the analog components and the

analog ground plane. Pins 11 through 24 are analog pins,

while all of the others are digital.

Noise Reduction Considerations

To minimize power supply noise, 0.1µF capacitors should be

placed as close as possible to the power supply pins, AVDD

and DVDD. Also, the layout should be designed using

separate digital and analog ground planes and these

capacitors should be terminated to the digital ground for

DVDD and to the analog ground for AVDD. Additional filtering

of the power supplies on the board is recommended.

Power Supplies

The DDS will provide the best SFDR (Spurious Free

Dynamic Range) when using +5V analog and +5V digital

power supply. The analog supply must be +5V (±10%). The

digital supply can be either a +3.3V (±10%) or a +5V (±10%)

supply, or anything in between. The DDS is rated to

125MSPS when using a +5V digital supply. The maximum

clock is 100MSPS when using a +3.3V digital supply.

Improving SFDR

As was previously noted, using +5V power supplies provides

the best SFDR. Under some clock and output frequency

combinations, particularly when the fCLK/fOUT ratio is less

than 4, the user can improve SFDR even further by

connecting the COMP2 pin (19) of the DDS to the analog

power supply. The digital supply must be +5V if this option is

explored. Improvements as much as 6dBc in the SFDR-to-

Nyquist measurement were seen in the lab.

FSK Modulation

BFSK (Binary Frequency Shift Keying) can be done by

enabling and disabling the offset frequency (ENOFR pin).

Once the offset frequency has been written once, it can be

toggled with a latency of 14 CLK cycles.

M-ary FSK or GFSK can be done by continuously loading in

new frequency words.

Quadrature Local Oscillators

Two HSP45314s can be used as sine/cosine generators for

quadrature local oscillator applications. It is important to note

that the Phase Accumulator feedback needs to be zeroed in

both devices if it is desired that both DDSs restart with a

known phase, which is determined by the use of the phase

control pins, PH1 and PH0. To zero the phase accumulator,

pull bit 5 of address 13 low and then high again at the same

time in both devices.

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