HSP45314 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HSP45314

CommLink™ Direct Digital Synthesizer

Intersil 

HSP45314

Control Register Descriptions (Continued)

ADDRESS

12

13

14

BITS

7:1

0

7:0

7

6

5

4:0

7:0

5:4

DESCRIPTION

Bits 7 through 1 are Intersil reserved for future serial input control. Do Not Change.

Center Frequency Enable. 1 = enable, 0 = center frequency disabled.

This bit can be used to zero the center frequency (CF(47:0)) to the phase accumulator. This does not zero

the processor interface registers - just the data path from the registers to the phase accumulator.

NCO control word.

Intersil reserved. Do Not Change.

Intersil Reserved. Do Not Change. Future Serial output frequency register enable.

Phase accumulator feedback. 0 = accumulator feedback disabled, 1 = accumulator enabled.

Intersil reserved. Do Not Change.

User should write 30 h to address 14 after RESET.

NCO-to-DAC setup and hold time control. Set to 11b.

RESET

STATE

00 h

1b

F8 h

1b

1b

1b

11000 b

10 h

01 b

14

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