HSP45314 Ver la hoja de datos (PDF) - Intersil

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HSP45314

CommLink™ Direct Digital Synthesizer

Intersil 

HSP45314

Control Pins

There are three control pins provided for phase and

frequency control. The PH0 and PH1 pins select phase

offsets of 0, 90, 180, and 270 degrees and can be used for

low speed, unfiltered BPSK or QPSK modulation. These

pins can also be used for providing sine/cosine when using

two HSP45314s together as quadrature local oscillators.

The ENOFR pin enables or zeros the offset frequency word

to the phase accumulator and can be used for FSK or MSK

modulation. These control pins and the UPDATE pin are

passed through special cells to minimize the probability of

meta-stability.

Reset

A RESET pin is available which resets all registers to their

defaults. In order to reset the part, the user must take the

RESET pin low, allow at least one CLK rising edge, and then

take the RESET pin high again. The latency from the RESET

pin going high until the output reflects the reset is 11 CLK

cycles. See the register description table in the back of the

datasheet for the default states of all bits in all addresses.

After RESET goes high, one rising edge of CLK is required

before the control registers can be written to again.

Comparator

A comparator is provided for square wave output generation.

The user can take the DDS analog output, filter it, and then

send it back into the comparator. A square wave will be

generated at the comparator output (COMPOUT pin) at an

amplitude level that is dependent on the digital power supply

used (DVDD). The comparator was designed to operate at

speeds comparable to the DDS output frequency range

(approximately 0-50MHz). It is not intended for low jitter

applications. The comparator has a sleep mode that is

activated by connecting both inputs (IN- and IN+) to the

analog power supply plane. This will save approximately

4mA of current (as shown in the Typical Application Circuit).

If the comparator is not used, leave the COMPOUT pin

floating.

DAC Voltage Reference

The internal voltage reference for the DAC has a nominal

value of +1.2V with a ±60ppm/oC drift coefficient over the

full temperature range of the converter. It is recommended

that a 0.1µF capacitor be placed as close as possible to the

REFIO pin, connected to the analog ground. The REFLO pin

(11) selects the reference. The internal reference can be

selected if pin 11 is tied low (ground). If an external reference

is desired, then pin 11 should be tied high (the analog supply

voltage) and the external reference driven into REFIO, pin

12. The full scale output current of the converter is a function

of the voltage reference used and the value of RSET. IOUT

should be within the 2mA to 20mA range, though operation

below 2mA is possible, with performance degradation.

If the internal reference is used, VFSADJ will equal

approximately 1.2V (pin 13). If an external reference is used,

VFSADJ will equal the external reference. The calculation for

IOUT (Full Scale) is:

IOUT(Full Scale) = (VFSADJ/RSET) X 32.

Analog Output

IOUTA and IOUTB are complementary current outputs. They

are generated by a 14-bit digital-to-analog converter (DAC)

that is capable of running at the full 125MSPS rate. The DDS

clock also clocks the DAC. The sum of the two output

currents is always equal to the full scale output current

minus one LSB. If single ended use is desired, a load

resistor can be used to convert the output current to a

voltage. It is recommended that the unused output be either

grounded or equally terminated. The voltage developed at

the output must not violate the output voltage compliance

range of -1.0V to 1.25V. RLOAD (the impedance loading

each current output) should be chosen so that the desired

output voltage is produced in conjunction with the output full

scale current. If a known line impedance is to be driven, then

the output load resistor should be chosen to match this

impedance. The output voltage equation is:

VOUT = IOUT X RLOAD.

These outputs can be used in a differential-to-single-ended

arrangement. This is typically done to achieve better

harmonic rejection. Because of a mismatch in IOUTA and

IOUTB, the transformer does not improve the harmonic

rejection. However, it can provide voltage gain without

adding distortion. The SFDR measurements in this data

sheet were performed with a 1:1 transformer on the output of

the DDS (see Figure 1). With the center tap grounded, the

output swing of pins 17 and 18 will be biased at zero volts.

The loading as shown in Figure 1 will result in a 500mVP-P

signal at the output of the transformer if the full scale output

current of the DAC is set to 20mA.

REQ IS THE IMPEDANCE

LOADING EACH OUTPUT

PIN 17

50Ω

IOUTB

100Ω

PIN 18

HSP45314

IOUTA

50Ω

VOUT = (2 x IOUT x REQ)VPP

50Ω

FIGURE 1.

50Ω REPRESENTS THE

SPECTRUM ANALYZER

VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. Allowing the

center tap to float will result in identical transformer output,

however the output pins of the DAC will have positive DC

offset, which could limit the voltage swing available due to

the output voltage compliance range. The 50Ω load on the

output of the transformer represents the load at the end of a

‘transmission line’, typically a spectrum analyzer,

oscilloscope, or the next function in the signal chain. The

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