TTRN012G7 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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TTRN012G7
Agere -> LSI Corporation
TTRN012G7 Datasheet PDF : 22 Pages
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TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Preliminary Data Sheet
August 2000
Pin Information (continued)
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals
Note: In Table 2, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 155 Mbits/s should be inter-
preted as 155.52 Mbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,
155 Mbits/s should be interpreted as 166.62 Mbits/s. (A similar interpretation should be made for 155 MHz.)
Pin
Symbol* Type† Level
Name/Description
99
D15P
I LVPECL Data Input (155 Mbits/s). 155 Mbits/s differential data input.
98
D15N
D15 is the most significant bit and is transmitted first on the
97
D14P
LVPECL D2G5P/N output.
96
D14N
94
D13P
LVPECL
93
D13N
92
D12P
LVPECL
91
D12N
89
D11P
LVPECL
88
D11N
87
D10P
LVPECL
86
D10N
84
D9P
LVPECL
83
D9N
82
D8P
LVPECL
81
D8N
79
D7P
LVPECL
78
D7N
77
D6P
LVPECL
76
D6N
74
D5P
LVPECL
73
D5N
72
D4P
LVPECL
71
D4N
69
D3P
LVPECL
68
D3N
67
D2P
LVPECL
66
D2N
62
D1P
LVPECL
61
D1N
60
D0P
LVPECL
59
D0N
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. Iu indicates an internal pull-up resistor on this pin.
6
Lucent Technologies Inc.
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