M80C186 Ver la hoja de datos (PDF) - Intel

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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

WAVEFORMS (Continued)

MAJOR CYCLE TIMING (Continued)

M80C186

270500 – 17

NOTES

1 The data hold time last only until INTA goes inactive even if the INTA transition occurs prior to TCLDX (min)

2 INTA occurs one clock later in slave mode

3 Status inactive just prior to T4

4 Latched A1 and A2 have the same timings as PCS5 and PCS6

5 For Write cycle followed by Read

49

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