M80C186 Ver la hoja de datos (PDF) - Intel
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M80C186 Datasheet PDF : 59 Pages
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M80C186
AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
All timings are measured at 1 5V and 100 pF loading on CLKOUT unless otherwise noted
All output test conditions are with CL e 50 – 200 pF (10 MHz) and CL e 50 – 100 pF (12 5 MHz)
For AC tests input VIL e 0 45V and VIN e 2 4V except at X1 where VIH e VCC b 0 5V
Symbol
Parameter
M80C186-10
Min
Max
M80C186-12
Unit
Min
Max
Comments
M80C186 MASTER INTERFACE TIMING RESPONSES (Continued)
TCLRO
TCHQSV
TCHDX
TAVCH
TCLLV
Reset Delay
Queue Status Delay
Status Hold Time
Address Valid to
Clock High
LOCK Valid Invalid
Delay
48
40
ns
CL e 50 – 200 pF
28
28
ns
All outputs
(except TCLTMV)
5
5
ns
10 MHz
0
0
CL e 50 – 100 pF
All Outputs
5
45
5
40
ns
12 5 MHz
TDXDL
DEN Inactive to
0
DT R Low
0
ns
M80C186 CHIP-SELECT TIMING RESPONSES
TCLCSV
Chip-Select
Active Delay
45
33
ns
TCXCSX
Chip-Select Hold from TCLCH b 10
TCLCH b 10
ns
Command Inactive
TCHCSX
Chip-Select
Inactive Delay
5
40
5
36
ns
M80C186 CLKIN REQUIREMENTS Measurements taken with following conditions External clock input to X1 and X2 not
connected (float)
TCKIN
CLKIN Period
50
1000
40
TCKHL
CLKIN Fall Time
5
TCKLH
CLKIN Rise Time
5
TCLCK
CLKIN Low Time
23
18
TCHCK
CLKIN High Time
23
18
M80C186 CLKOUT TIMING 200 pF load maximum for 10 MHz or less
1000 ns
5
ns
3 5 to 1 0V(1)
5
ns
1 0 to 3 5V(1)
ns
1 5V(2)
ns
1 5V(2)
TCICO
CLKIN to
CLKOUT Skew
25
21
ns
TCLCL
TCLCH
CLKOUT Period
CLKOUT
Low Time (min)
100
2000
80
2000 ns
0 5 TCLCLb8
0 5 TCLCLb7
ns 1 5V
TCHCL
CLKOUT
High Time (min)
0 5 TCLCLb8
0 5 TCLCLb7
ns 1 5V
TCH1CH2
TCL2CL1
CLKOUT Rise Time
CLKOUT Fall Time
10
10
ns 1 0 to 3 5V
10
10
ns 3 5 to 1 0V
NOTE
1 These values are supplied for design purposes
2 TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 45% of TCKIN
47
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