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M80C186 Datasheet PDF : 59 Pages
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M80C186
Timer DMA 0 1 Control Register
These registers are the control words for all the in-
ternal interrupt sources The format for these regis-
ters is shown in Figure 28 The three bit positions
PR0 PR1 and PR2 represent the programmable pri-
ority level of the interrupt source The MSK bit inhib-
its interrupt requests from the interrupt source The
MSK bits in the individual control registers are the
exact same bits as are in the Mask Register modify-
ing them in the individual control registers will also
modify them in the Mask Register and vice versa
INT0-INT3 Control Registers
These registers are the control words for the four
external input pins Figure 29 shows the format of
the INT0 and INT1 Control registers Figure 30
shows the format of the INT2 and INT3 Control reg-
isters In cascade mode or special fully nested
mode the control words for INT2 and INT3 are not
used
The bits in the various control registers are encoded
as follows
PRO-2 Priority programming information Highest
Priority e 000 Lowest Priority e 111
LTM
Level-trigger mode bit 1 e level-triggered
0 e edge-triggered Interrupt Input levels
are active high In level-triggered mode an
interrupt is generated whenever the exter-
nal line is high In edge-triggered mode an
interrupt will be generated only when this
MSK
C
SFNM
level is preceded by an inactive-to-active
transition on the line In both cases the
level must remain active until the interrupt
is acknowledged
Mask bit 1 e mask 0 e non-mask
Cascade mode bit 1 e cascade 0 e di-
rect
Special fully nested mode bit 1 e SFNM
EOI Register
The end of the interrupt register is a command regis-
ter which can only be written into The format of this
register is shown in Figure 30 It initiates an EOI
command when written to by the M80C186 CPU
The bits in the EOI register are encoded as follows
Sx
Encoded information that specifies an in-
terrupt source vector type as shown in Ta-
ble 4 For example to reset the In-Service
bit for DMA channel 0 these bits should be
set to 01010 since the vector type for DMA
channel 0 is 10
NOTE
To reset the single In-Service bit for any of
the three timers the vector type for timer 0
(8) should be written in this register
NSPEC A bit that determines the type of EOI com-
SPEC mand Nonspecific e 1 Specific e 0
15 14
0
0
4
3
2
1
0
0 MSK PR2 PR1 PR0
Figure 28 Timer DMA Control Registers Formats
15 14
0
0
7
6
5
0 SFNM C
4
3
2
1
0
LTM MSK PR2 PR1 PR0
Figure 29 INT0 INT1 Control Register Formats
15 14
0
0
5
4
3
2
1
0
0 LTM MSK PR2 PR1 PR0
Figure 30 INT2 INT3 Control Register Formats
36
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