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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

15 14 13 12 11 10 9

8

7

6

5

4

M DESTINATION M SOURCE

IO DEC

INC IO DEC INC

TC

INT

SYN

T

D

P

R

Q

X e DON’T CARE

Figure 17 DMA Control Register

3

2

1

0

X

CHG ST B

NOCHG STOP W

DMA Channel Control Word Register

Each DMA Channel Control Word determines the

mode of operation for the particular M80C186 DMA

channel This register specifies

 the mode of synchronization

 whether bytes or words will be transferred

 whether interrupts will be generated after the last

transfer

 whether DMA activity will cease after a pro-

grammed number of DMA cycles

 the relative priority of the DMA channel with re-

spect to the other DMA channel

 whether the source pointer will be incremented

decremented or maintained constant after each

transfer

 whether the source pointer addresses memory or

I O space

 whether the destination pointer will be increment-

ed decremented or maintained constant after

each transfer and

 whether the destination pointer will address

memory or I O space

The DMA channel control registers may be changed

while the channel is operating However any chang-

es made during operation will affect the current DMA

transfer

DMA Control Word Bit Descriptions

BW

ST STOP

CHG NOCHG

INT

TC

Byte Word (0 1) Transfers

Start stop (1 0) Channel

Change Do not change (1 0)

ST STOP bit If this bit is set when

writing to the control word the

ST STOP bit will be programmed

by the write to the control word If

this bit is cleared when writing the

control word the ST STOP bit will

not be altered This bit is not

stored it will always be a 0 on

read

Enable Interrupts to CPU on

Transfer Count termination

If set DMA will terminate when

the contents of the Transfer Count

register reach zero The ST STOP

bit will also be reset at this point if

TC is set If this bit is cleared the

DMA unit will decrement the trans-

fer count register for each DMA

cycle but the DMA transfer will

not stop when the contents of the

TC register reach zero

SYN

00 No synchronization

NOTE

When unsynchronized transfers

are specified the TC bit will be ig-

nored and the ST bit will be

cleared upon the transfer count

reaching zero stopping the chan-

nel

(2 bits)

01 Source synchronization

10 Destination synchronization

11 Unused

SOURCE INC

Increment source pointer by 1 or 2

(depends on B W) after each

transfer

M IO Source pointer is in M IO space

(1 0)

DEC Decrement source pointer by 1 or

2 (depends on B W) after each

transfer

DEST

INC Increment destination pointer by 1

or 2 (B W) after each transfer

M IO Destination pointer is in M IO

space (1 0)

DEC Decrement destination pointer by

1 or 2 (depending on B W) after

each transfer

P

Channel priority relative to other

channel

0 low priority

1 high priority

Channels will alternate cycles if

both set at same priority level

TDRQ

0 Disable DMA requests from tim-

er 2

1 Enable DMA requests from tim-

er 2

Bit 3

Bit 3 is not used

26

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