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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

The lower limit of memory defined by this chip select

is always 0H while the upper limit is programmable

By programming the upper limit the size of the

memory block is also defined Table 8 shows the

relationship between the upper address selected

and the size of the memory block obtained

Table 8 LMCS Programming Values

Upper

Address

Memory

Block

Size

LMCS Value

(Assuming

R0eR1eR2e0)

003FFH

007FFH

00FFFH

01FFFH

03FFFH

07FFFH

0FFFFH

1FFFFH

3FFFFH

1K

2K

4K

8K

16K

32K

64K

128K

256K

0038H

0078H

00F8H

01F8H

03F8H

07F8H

0FF8H

1FF8H

3FF8H

The upper limit of this memory block is defined in the

LMCS register (see Figure 12) This register is at

offset A2H in the internal control block The legal

values for bits 6– 15 and the resulting upper address

and memory block sizes are given in Table 8 Any

combination of bits 6– 15 not shown in Table 8 will

result in undefined operation After reset the LMCS

register value is undefined However the LCS chip-

select line will not become active until the LMCS

register is accessed

Any internally generated 20-bit address whose up-

per 16 bits are less than or equal to LMCS (with bits

0–5 ‘‘1’’) will cause LCS to be active LMCS register

bits R2–R0 are used to specify the READY mode for

the area of memory defined by this chip-select regis-

ter

Mid-Range Memory CS

The M80C186 provides four MCS lines which are

active within a user-locatable memory block This

block can be located within the M80C186 1M byte

memory address space exclusive of the areas de-

fined by UCS and LCS Both the base ad-

dress and size of this memory block are programma-

ble

The size of the memory block defined by the mid-

range select lines as shown in Table 9 is deter-

mined by bits 8 – 14 of the MPCS register (see Figure

13) This register is at location A8H in the internal

control block One and only one of bits 8 – 14 must

be set at a time Unpredictable operation of the MCS

lines will otherwise occur Each of the four chip-se-

lect lines is active for one of the four equal contigu-

ous divisions of the mid-range block Thus if the to-

tal block size is 32K each chip select is active for 8K

of memory with MCS0 being active for the first range

and MCS3 being active for the last range

The EX and MS in MPCS relate to peripheral func-

tionally as described in a later section

Table 9 MPCS Programming Values

Total Block

Size

Individual

Select Size

MPCS Bits

14 – 8

8K

16K

32K

64K

128K

256K

512K

2K

4K

8K

16K

32K

64K

128K

0000001B

0000010B

0000100B

0001000B

0010000B

0100000B

1000000B

The base address of the mid-range memory block is

defined by bits 15 – 9 of the MMCS register (see Fig-

ure 14) This register is at offset A6H in the internal

control block These bits correspond to bits

A19 – A13 of the 20-bit memory address Bits

A12 – A0 of the base address are always 0 The base

address may be set at any integer multiple of the

size of the total memory block selected For exam-

ple if the mid-range block size is 32K (or the size of

the block for which each MCS line is active is 8K)

the block could be located at 10000H or 18000H

but not at 14000H since the first few integer multi-

ples of a 32K memory block are 0H 8000H

10000H 18000H etc After reset the contents of

both of these registers is undefined However none

of the MCS lines will be active until both the MMCS

and MPCS registers are accessed

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET A0H 1 1 U U U U U U U U 1 1 1 R2 R1 R0

A19

A11

Figure 11 UMCS Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET A2H 0 0 U U U U U U U U 1 1 1 R2 R1 R0

A19

A11

Figure 12 LMCS Register

22

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