T431616B Ver la hoja de datos (PDF) - Taiwan Memory Technology

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componentes Descripción

Fabricante

T431616B

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616B

DC CHARACTERISTICS

TA = -10 to +85°C , VIH(min)/VIL(max)=2.0V/0.8V

Parameter Symbol

MAX.

Unit

Test Condition

Note

Operating Current

( One Bank

ICC1

Active)

Burst Length = 1

120

mA tRC≥tRC(min) ,tCC≥tCC(min),IOL= 0 mA

1,3

Precharge Standby ICC2 P

Current in power-

down mode

ICC2 PS

2

CKE ≤ VIL(max),tCC=15ns

mA

3

2

CKE ≤ VIL(max),CLK ≤ VIL(max), tCC =∞

Precharge Standby

ICC2 N

30

Current in non

CKE ≥ VIH(min), CS ≥ VIH(min),tCC=15ns

Input signals are changed one time during 30ns

power-down mode

ICC2 NS

mA

3

CKE≥VIH(min),CLK ≤ VIL(min),tCC=∞

2

Input signals are stable

Active Standby ICC3 P

Current in power-

down mode

ICC3 PS

10

CKE ≤ VIL(max),tCC=15ns

mA

3

10

CKE ≤ VIL(max),CLK ≤ VIL(max),tCC=∞

Active Standby

CKE≥VIH(min), CS ≥VIH(min),tCC=15ns

Current in non

ICC3 N

40

Input signals are changed one time during 30ns

power-down mode

mA

3

CKE≥VIH(min),CLK ≤ VIL(min),tCC=∞

(One Bank Active) ICC3 NS

10

Input signals are stable

Operating Current

(Burst Mode)

ICC4

140

CAS Latency 3 IOL=0 mA,Page Burst

mA

All Band Activated

1,3

140

CAS Latency 2

tCCD= tCCD(min)

Refresh Current ICC5

140

mA tRC ≥tRC(min)

2,3

Self refresh

Current

ICC6

1

mA CKE ≤ 0.2V

Note:

1. Measured with output open. Addresses are changed only one time during tCC(min) .

2. Refresh period is 32ms. Addresses are changed only one time during tCC(min) .

3. tCC : Clock cycle time.

tRC : Row cycle time.

tCCD : Column address to column address delay time.

Taiwan Memory Technology, Inc. reserves the right P. 6

to change products or specifications without notice.

Publication Date: JUL. 2001

Revision:A

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