T431616B Ver la hoja de datos (PDF) - Taiwan Memory Technology

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T431616B

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616B

Read & Write Cycle at Same Bank @Burst Length = 4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

t RCD

*Note1

tR C

HIGH

*Note2

ADDR

Ra

Ca0

Rb

Cb0

BA

A10/AP

Ra

CL=2

DQ

CL=3

WE

tR A C

*Note3

*Note3

Rb

tOH

Qa0 Qa1 Qa2 Qa3

t SAC

t OH

t SHZ

*Note4

Qa0 Qa1 Qa2 Qa3

tSAC

t SHZ

*Note4

Db0 Db1 Db2 Db3

tRDL

Db0 Db1 Db2 Db3

tRDL

DQM

Row

Active (A-

Bank)

Read (A-

Bank)

Precharg

e (A-

Bank)

Row Active

(A-Bnak)

Write (A-

Bnak)

Precharge

(a-Bnak)

:Don't care

*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is

available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3. Access time from Row active command. tCC*(tRCD+CAS latency-1)+tSAC

4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)Burst can’t end in Full Page Mode.

Taiwan Memory Technology, Inc. reserves the right P.17

to change products or specifications without notice.

Publication Date: JUL. 2001

Revision:A

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