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SC417EVB

10A Integrated FET Regulator with Programmable LDO

Semtech Corporation 

SC417/SC427

Applications Information (continued)

IPEAK

ILOAD

ILIM

Time

Figure 8 — Valley Current Limit

Setting the valley current limit to 10A results in a peak

inductor current of 10A plus peak ripple current. In this

situation, the average (load) current through the inductor

is 10A plus one-half the peak-to-peak ripple current.

The internal 10μA current source is temperature compen-

sated at 4100ppm in order to provide tracking with the

RDS .

(ON)

The RILIM value is calculated by the following equation.

RILIM = 735 x ILIM

Note that because the low-side MOSFET with low RDS

(ON)

is used for current sensing, the PCB layout, solder connec-

tions, and PCB connection to the LX node must be done

carefully to obtain good results. Refer to the layout guide-

lines for information.

Soft-Start of PWM Regulator

Soft-start is achieved in the PWM regulator by using an

internal voltage ramp as the reference for the FB

Comparator. The voltage ramp is generated using an

internal charge pump which drives the reference from

zero to 500mV in ~1.2mV increments, using an internal

~500kHz oscillator. When the ramp voltage reaches

500mV, the ramp is ignored and the FB comparator

switches over to a fixed 500mV threshold. During soft-start

the output voltage tracks the internal ramp, which limits

the start-up inrush current and provides a controlled soft-

start profile for a wide range of applications. Typical soft-

start ramp time is 850μs.

During soft-start the regulator turns off the low-side

MOSFET on any cycle if the inductor current falls to zero.

This prevents negative inductor current, allowing the

device to start into a pre-biased output.

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage

is 10% below the nominal voltage, PGOOD is pulled low. It

is held low until the output voltage returns above -8% of

nominal. PGOOD is held low during start-up and will not

be allowed to transition high until soft-start is completed

(when V reaches 500mV) and typically 2ms has passed.

FB

PGOOD will transition low if the V pin exceeds +20% of

FB

nominal, which is also the over-voltage shutdown thresh-

old (600mV). PGOOD also pulls low if the EN/PSV pin is

low when V5V is present.

Output Over-Voltage Protection

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 500mV + 20%

(600mV). When V exceeds the OVP threshold, DL latches

FB

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN/PSV input

is toggled or V5V is cycled. There is a 5μs delay built into

the OVP detector to prevent false transitions. PGOOD is

also low after an OVP event.

Output Under-Voltage Protection

When V falls 25% below its nominal voltage (falls to

FB

375mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tri-

state the MOSFETs. The controller stays off until EN/PSV is

toggled or V5V is cycled.

V5V UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-

ing and tri-states the DH/DL drivers until V5V rises above

3.9V. An internal Power-On Reset (POR) occurs when V5V

exceeds 3.9V, which resets the fault latch and soft-start

counter to prepare for soft-start. The SC417/SC427 then

begins a soft-start cycle. The PWM will shut off if V5V falls

below 3.6V.

LDO Regulator

The device features an integrated LDO regulator with a

programmable output voltage from 0.75V to 5.25V using

17

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