S3C2440X Ver la hoja de datos (PDF) - Samsung

Número de pieza

componentes Descripción

Fabricante

S3C2440X

32-bit RISC microprocessor.

Samsung 

2003.10.15

ELECTRICAL DATA

S3C2440X RISC MICROPROCESSOR

Table 25-14. IIC BUS Controller Module Signal Timing

(VDD = 1.8 V ± 0.15 V, TA = 0 to 70 °C, VEXT = 3.3V ± 0.3V)

Parameter

Symbol

Min

SCL clock frequency

fSCL

–

Typ.

–

SCL high level pulse width

SCL low level pulse width

Bus free time between STOP and START

START hold time

SDA hold time

SDA setup time

STOP setup time

tSCLHIGH

std. 4.0

–

fast 0.6

tSCLLOW

std. 4.7

–

fast 1.3

tBUF

std. 4.7

–

fast 1.3

tSTARTS

std. 4.0

–

fast 0.6

tSDAH

std. 0

–

fast 0

tSDAS

std. 250

–

fast 100

tSTOPH

std. 4.0

–

fast 0.6

NOTES: Std. means Standard Mode and fast means Fast Mode.

1. The IIC data hold time(tSDAH) is minimum 0ns.

(IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.)

Please check the data hold time of your IIC device if it's 0 nS or not.

2. The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device.

Max

std. 100

fast 400

–

–

–

–

std. - fast

0.9

–

–

Unit

kHz

µs

µs

µs

µs

µs

ns

µs

Table 25-15. SD/MMC Interface Transmit/Receive Timing Constants

(VDD = 1.2 V ± 0.1 V, TA = 0 to 70 °C, VEXT = 3.3V ± 0.3V)

Parameter

Symbol

Min

SD Command output Delay time

tSDCD

0

SD Command input Setup time

tSDCS

5

SD Command input Hold time

tSDCH

0

SD Data output Delay time

tSDDD

0

SD Data input Setup time

tSDDS

5

SD Data input Hold time

tSDDH

0

Typ.

–

–

–

–

–

–

Max

1

11

1

1

11

1

Unit

ns

ns

ns

ns

ns

ns

25-36

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.

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