HI7188(2000) Ver la hoja de datos (PDF) - Intersil

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componentes Descripción

Fabricante

HI7188
(Rev.:2000)

8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System

Intersil 

HI7188

Electrical Specifications

AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND, VCM = AGND, PGIA Gain = 1,

OSCIN = 3.6864MHz, Bipolar Input Range Selected (Continued)

-40oC TO 85oC

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS

SCLK Minimum Cycle Time, tSCLK

(Notes 2, 7)

SCLK Minimum Pulse Width, tSCLKPW (Notes 2, 7)

CS to SCLK Precharge Time, tPRE

(Notes 2, 7)

Data Setup to SCLK Rising Edge (Write), (Notes 2, 7)

tDSU

Data Hold from SCLK Rising Edge

(Write), tDHLD

(Notes 2, 7)

Data Read Access from Instruction Byte (Notes 2, 7)

Write, tACC

Read Bit Valid from SCLK Falling Edge, (Notes 2, 7)

tDV

Last Data Transfer to Data Ready

Inactive, tDRDY

(Notes 2, 7)

RESET Low Pulse Width tRESET

(Notes 2, 7)

RSTI/O Low Pulse Width tRSTI/O

(Notes 2, 7)

MUX High Pulse Width tMUX

(Notes 2, 7)

CADDR Valid to MUX High

(Notes 2, 7)

200

-

60

-

50

-

50

-

0

-

-

-

-

-

-

50

100

-

100

-

14

-

-

-

-

ns

-

ns

-

ns

-

ns

-

ns

40

ns

40

ns

-

ns

-

ns

-

ns

-

µs

75

ns

Oscillator Clock Frequency

(Notes 2, 7)

-

3.6864

-

MHz

Output Rise/Fall Time

(Notes 2, 7)

-

-

30

ns

Input Rise/Fall Time

(Notes 2, 7)

-

-

1

µs

POWER SUPPLY CHARACTERISTICS

IAVDD

IAVSS

IDVDD

Power Dissipation, Active PDA

AVDD = +5V, OSC1 = 3.6864MHz (Note 3)

-

AVSS = -5V, OSC1 = 3.6864MHz (Note 3)

-

DVDD = +5V, SCLK = 4MHz

-

AVDD = +5V, AVSS = -5V, SLP = ‘0’

-

(Notes 3, 9)

1.8

3.0

mA

1.8

3.0

mA

2.0

4.0

mA

28

50

mW

Power Dissipation, Sleep PDS

AVDD = +5V, AVSS = -5V, SLP = ‘1’

(Notes 3, 9)

-

5

-

mW

PSRR (∆ Vsupply = 0.25V)

PSRR = 20log (∆Vsupply / ∆VOS) (Note 3)

-

75

NOTES:

2. Parameter guaranteed by design or characterization, not production tested.

3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges.

4. These errors can be removed by re-calibrating at the desired operating temperature.

5. Applies after system calibration.

6. Fully differential input signal source is used.

7. See Load Test Circuit, Figure 1, R1 = 10kΩ, CL = 50pF (Includes Stray and Jig Capacitance).

8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz.

9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).

-

dB

7

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