HI7188(2000) Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
HI7188 Datasheet PDF : 24 Pages
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HI7188
Pin Descriptions
44 LEAD
MQFP
41
42
43
44
1
2
3, 30
4, 29, 39
5, 6, 27, 28
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
31
32
33
34
35
36
37
38
40
PIN NAME
MODE
SCLK
SDO
SDIO
OSC1
OSC2
DVDD
DGND
AVSS
VINL1
VINH1
VINL2
VINH2
VINL3
VINH3
VINL4
VINH4
VINL5
VINH5
VINL6
VINH6
VINL7
VINH7
VINL8
VINH8
VCM
VRLO
VRHI
AVDD
RST
CA
MXC
A0
A1
A2
EOS
RSTI/O
CS
PIN DESCRIPTION
Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous External Clocking
(MODE = 0) for the Serial Port.
Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling
edge.
Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial
Peripheral Interface.
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
Oscillator clock input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the
device, or an external oscillator can drive OSC1. The oscillator frequency should be 3.6864MHz to maintain Line
Noise Rejection.
Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise.
Positive Digital supply (+5V).
Digital supply ground.
Negative analog power supply (-5V).
Analog input low for Channel 1.
Analog input high for Channel 1.
Analog input low for Channel 2.
Analog input high for Channel 2.
Analog input low for Channel 3.
Analog input high for Channel 3.
Analog input low for Channel 4.
Analog input high for Channel 4.
Analog input low for Channel 5.
Analog input high for Channel 5.
Analog input low for Channel 6.
Analog input high for Channel 6.
Analog input low for Channel 7.
Analog input high for Channel 7.
Analog input low for Channel 8.
Analog input high for Channel 8.
Common mode voltage. Must be tied to the mid point of AVDD and AVSS.
External reference input. Should be negative referenced to VRHI.
External reference input. Should be positive referenced to VRLO.
Positive analog power supply (+5V).
Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines.
Calibration active output. Indicates that at least one active channel is in a calibration mode.
Multiplexer control output. Indicates that the conversion for the active channel is complete.
Logical channel count output (LSB).
Logical channel count output.
Logical channel count output (MSB).
End of scan output. Signals the end of a channel scan (all active channels have been converted) and data is
available to be read. Remains low until data RAM is read.
I/O reset (active low) input. Resets serial interface state machine only.
Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are
three-state.
5
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