HI7188(2000) Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Fabricante
HI7188 Datasheet PDF : 24 Pages
| |||
HI7188
Absolute Maximum Ratings
Supply Voltage
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS to AVDD
Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DVDD
ESD Tolerance (No Damage)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND, VCM = AGND, PGIA Gain = 1,
OSCIN = 3.6864MHz, Bipolar Input Range Selected
-40oC TO 85oC
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
Dependent on Gain (Note 2)
-
-
16
Bits
Integral Non-Linearity, INL
FS = 25Hz, +FS, +MS, 0, -MS, -FS
End Point Line Method (Notes 3, 5, 6)
-
±0.0015
±0.0045
%FS
Differential Non-Linearity
(Note 2)
No Missing Codes to 16-Bits
-
Offset Error, VOS (Calibrated)
Full Scale Error, FSE (Calibrated)
Gain Error (Calibrated)
VINHI = VINLO (Notes 3, 4)
VINHI - VINLO = +2.5V (Notes 3, 4)
Slope = +Full Scale - (-Full Scale)
(Notes 3, 4)
-
±0.0015
-
-
±0.0015
-
-
±0.0015
-
%FS
%FS
%FS
Noise, VN(P-P)
Common Mode Rejection Ratio,
CMRR
VCM = 0V (Note 5) Delta VCM = ±3V
-
1/4
-
LSB
-
-75
-
dB
Off Channel Isolation
(Note 2)
-120
-
-
dB
ANALOG INPUT
Common Mode Input Range, VCM
Input Leakage Current, IIN
Input Capacitance, CIN
DIGITAL INPUTS
(Note 2)
VIN = AVDD (Note 3)
(Note 2) See Table 2
AVSS
-
AVDD
-
-
-
1.0
nA
-
4.0
-
pF
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic Current, II
Input Capacitance, CIN
DIGITAL CMOS OUTPUTS
VIN = 0V, +5V
VIN = 0V (Note 2)
2.0
-
-
V
-
-
0.8
V
-
1.0
10
µA
-
5.0
-
pF
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Three-State Leakage
Current, IOZ
Digital Output Capacitance, COUT
IOUT = -100µA (Note 7)
IOUT = 3.2mA (Note 7)
VOUT = 0V, +5V (Note 7)
(Note 2)
2.4
-
-
V
-
-
0.4
V
-
1
10
µA
-
10
-
pF
6
Share Link: 