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Fabricante

PCF2113

LCD controllers/drivers

NXP Semiconductors. 

NXP Semiconductors

PCF2113x

LCD controllers/drivers

Table 6. Bias levels as a function of multiplex rate

Multiplex Number Bias voltages[1]

rate

of levels V1

V2

V3

V4

V5

V6

1:18

5

VLCD

3⁄4

1⁄2

1⁄2

1⁄4

VSS

1:9

5

VLCD

3⁄4

1⁄2

1⁄2

1⁄4

VSS

1:2

4

VLCD

2⁄3

2⁄3

1⁄3

1⁄3

VSS

[1] The values in the table are given relative to VLCD − VSS, e.g. 3⁄4 means {3⁄4 × (VLCD − VSS)} + VSS.

8.3 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external

components are required and the OSC pin must be connected to VDD1.

8.4 External clock

If an external clock is to be used, this input is at the OSC pin. The resulting display frame

frequency is given by:

f fr (LCD)

=

--f---o--s--c--

3072

Only in the Power-down mode is the clock allowed to be stopped (pin OSC connected to

VSS), otherwise the LCD is frozen in a DC state.

8.5 Power-on reset

The on-chip power-on reset block initializes the chip after power-on or power failure. This

is a synchronous reset and requires 3 oscillator cycles to be executed.

8.6 Registers

The PCF2113x has two 8-bit registers: an Instruction Register (IR) and a Data

Register (DR). The Register Select (RS) signal determines which register will be

accessed. The instruction register stores instruction codes such as ‘display clear’, ‘cursor

shift’, and address information for the Display Data RAM (DDRAM) and Character

Generator RAM (CGRAM). The instruction register can be written to but not read from by

the system controller.

The data register temporarily stores data to be read from the DDRAM and CGRAM. When

reading, data from the DDRAM or CGRAM corresponding to the address in the instruction

register is written to the data register prior to being read by the ‘read data’ instruction.

8.7 Busy flag

The busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the

chip is busy and further instructions will not be accepted. The busy flag is output to

pin DB7 when bit RS = 0 and bit R/W = 1. Instructions must only be written after checking

that the busy flag is at logic 0 or waiting for the required number of cycles.

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

© NXP B.V. 2008. All rights reserved.

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