PCF8531 Ver la hoja de datos (PDF) - Philips Electronics

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PCF8531

34 × 128 pixel matrix driver

Philips Electronics 

Philips Semiconductors

34 × 128 pixel matrix driver

Product specification

PCF8531

8.17 Addressing

Data is written in bytes into the RAM matrix of the

PCF8531 as illustrated in Figs 5, 6 and 7. The display

RAM has a matrix of 34 × 128 bits. The columns are

addressed by the address pointer. The address ranges are

X 0 to X 127 (7FH) and Y 0 to Y 5 (5H). Addresses

outside of these ranges are not allowed. In vertical

addressing mode (V = 1), the Y address increments after

each byte (see Fig.6). After the last Y address (Y = 4),

Y wraps around to 0 and X increments to address the next

column. In horizontal addressing mode (V = 0), the

X address increments after each byte (see Fig.7). After the

last X address (X = 127), X wraps around to 0 and

Y increments to address the next row. After the very last

address (X = 127 and Y = 4), the address pointers wrap

around to address (X = 0 and Y = 0). It should be noted

that in bank 4 only the LSB (DB0) of the data will be written

into the RAM. The Y address 5 is reserved for icon data

and is not affected by the addressing mode; it should be

noted that in bank 5 only the 5th data bit (DB4) will be

written into the RAM.

handbook, full paLgSewBidth

MSB

LSB

MSB

LSB

MSB

icon data

0

X address

127

Fig.5 RAM format and addressing.

0

1

2

Y address

3

4

5

MGS469

handbook, full pagewidth

0

5

1

6

2

3

4

0

1

icon data

0

1

2

Y address

3

638

4

639

5

0

X address

127

MGS470

Fig.6 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

2000 Feb 11

11

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