MS81V04160-25TB Ver la hoja de datos (PDF) - Oki Electric Industry

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Fabricante

MS81V04160-25TB

Dual FIFO (262,214-word x 8-Bits) x 2

Oki Electric Industry 

MS81V04160

OKI Semiconductor

OPERATION MODE

Write Operation Cycle (MODE2=Vss)

The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,

WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding

WE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be

preformed for internal circuit initialization before Write operation.

Each write operation, which begins after RSTW1, must contain at least 80 active write

cycles, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM

array, which at that time is stored in the serial data registers attached to the DRAM array, an

RSTW1 operation is required after the last SWCK cycle.

Note that every write timing of MS8104160 is delayed by one clock compared with read

timings for easy cascading without any interface delay devices.

Setting MODE1 to the Vss level starts write data accessing in the cycle in which RSTW1,

WE1, and IE1 control signals are input.

Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the

cycle in which RSTW1, WE1, and IE1 control signals are input.

These operation are the same for Port1 and Port2.

Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and

Data input.

WE1,2

H

H

L

IE1,2

H

L

X

Internal Write address pointer

Data input

Incremented

Input

Halted

Not input

X indicates "don't care"

Write Operation Cycle (MODE2=Vcc)

The write Operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1,

WE2, and IE1, IE2. Port1 write operation is accomplished by cycling SWCK and holding

both WE1 and IE1 low after the write address pointer reset operation or RSTW1. RSTW1

must be performed for internal circuit initialization before write operation.

Each write operation, which begins after RSTW1, must contain at least 80 active write

cycle, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM

array, which at that time is stored in the serial data registers attached to the DRAM array,

an RSTW1 operation is required after the last SWCK cycle.

Note that every write timing of MS8104160 is delayed by one clock compared with read

timings for easy cascading without any interface delay devices.

Setting MODE1 to the Vss level starts write data accessing in the cycle in which

RSTW1.WE1, and IE1 control signals are input.

Setting MODE1 to the Vcc level starts write data accessing in the cycle in which RSTW1,

WE1, and IE1 control signals are input.

Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the

cycle in which RSTW1, WE1, and IE1 control signals are input.

These operations are the same for port1 and Port2.

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