MS81V04160-25TB Ver la hoja de datos (PDF) - Oki Electric Industry
Número de pieza
componentes Descripción
Fabricante
MS81V04160-25TB Datasheet PDF : 22 Pages
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MS81V04160
OKI Semiconductor
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data
input.
WE1,2
L
L
H
IE1,2
L
H
X
Internal Write address pointer
Data input
Incremented
Input
Halted
Not input
X indicates "don't care"
Read Operation Cycle (MODE2=Vss)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1,
RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding
both RE1 and OE1 high after the read address pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 80 active read
cycles, i.e. SRCK cycles while RE1 and OE1 are high.
These operations are the same for Port1 and Port2.
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data
output.
RE1,2
H
H
L
L
OE1,2
H
L
H
L
Internal Write address pointer
Incremented
Halted
Data output
Output
High impedance
Output
High impedance
Read Operation Cycle (MODE2=Vcc)
The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1,
RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding
both RE1 and OE1 high after the read address pointer reset operation or RSTR1.
Each read operation, which begins after RSTR1, must contain at least 80 active read
cycles, i.e. SRCK cycles while RE1 and OE1 are low.
These operations are the same for Port1 and Port2.
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data
output.
RE1,2
L
L
H
H
OE1,2
L
H
L
H
Internal Write address pointer
Incremented
Halted
Data output
Output
High impedance
Output
High impedance
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