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MPC8544E
(Rev.:2009)

PowerQUICC™ III Integrated Processor Hardware Specifications

Freescale Semiconductor 

DDR and DDR2 SDRAM

Figure 3 shows the DDR SDRAM input timing diagram.

MCK[n]

MCK[n]

tMCK

MDQS[n]

MDQ[x]

tDISKEW

D0

D1

tDISKEW

Figure 3. DDR SDRAM Input Timing Diagram (tDISKEW)

6.2.2 DDR SDRAM Output AC Timing Specifications

Table 18 provides the output AC timing specifications for the DDR SDRAM interface.

Table 18. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol1

Min

Max

Unit

MCK[n] cycle time, MCK[n]/MCK[n] crossing

ADDR/CMD output setup with respect to MCK

533 MHz

400 MHz

333 MHz

ADDR/CMD output hold with respect to MCK

533 MHz

400 MHz

333 MHz

MCS[n] output setup with respect to MCK

533 MHz

400 MHz

333 MHz

MCS[n] output hold with respect to MCK

533 MHz

400 MHz

333 MHz

MCK to MDQS Skew

tMCK

tDDKHAS

tDDKHAX

tDDKHCS

tDDKHCX

tDDKHMH

3.75

1.48

1.95

2.40

1.48

1.95

2.40

1.48

1.95

2.40

1.48

1.95

2.40

–0.6

6

ns

ns

—

—

—

ns

—

—

—

ns

—

—

—

ns

—

—

—

0.6

ns

Notes

2

3

7

3

7

—

—

3

7

—

—

3

7

—

—

4

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

20

Freescale Semiconductor

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